Hazards (static and dynamic) in combinational logic

3.3.14 · Hardware › Combinational Circuits

Hazards exist kyun karte hain?

Classic culprit: ek input output ko directly aur ek inverter ke through dono taraf se feed karta hai. Inverter delay add karta hai, toh ek short window ke liye ek signal aur "NOT woh signal" dono ek jaise dikhte hain (dono 0 ya dono 1).

Types kya hote hain?

Static-1 hazard kaise arise karta hai? (Scratch se derivation)

Function lo $F = A B + \overset{ˉ}{B} C$

Setup. $A = 1$ , $C = 1$ hold karo, aur $B$ ko $1 \to 0$ change hone do.

$B = 1$ ke saath: $F = (1) (1) + (0) (1) = 1$ .
$B = 0$ ke saath: $F = (1) (0) + (1) (1) = 1$ .

Toh $F$ 1 rehna chahiye. Ab paths ko trace karo jab $B$ fall kar raha ho:

Term $A B$ : jab $B \to 0$ , $A B \to 0$ immediately ( $B$ directly AND ko feed karta hai).
Term $\overset{ˉ}{B} C$ : isko $\overset{ˉ}{B}$ chahiye, jo ek inverter se compute hota hai. Toh $\overset{ˉ}{B}$ ek gate-delay baad $0 \to 1$ jaata hai. Tab tak $\overset{ˉ}{B} C = 0$ .

Bad window: ek inverter-delay ke liye, $A B$ pehle hi 0 ho chuka hai lekin $\overset{ˉ}{B} C$ abhi tak 1 nahi hua. Dono product terms $0$ hain → $F$ momentarily $= 0$ . Yahi hai glitch $1 \to 0 \to 1$ .

Figure — Hazards (static and dynamic) in combinational logic

Worked Examples

Common Mistakes

The 80/20 core

Flashcards

Combinational logic mein hazard kya hota hai?

Ek input transition ke dauran momentary incorrect output (glitch), jo reconvergent paths par unequal propagation delays ki wajah se hota hai; steady-state output phir bhi correct hota hai.

Fundamentally hazard kis cheez se hota hai?

Ek input output tak do (ya zyada) alag delay wale paths se pahunchta hai (classically direct vs. inverter ke through).

Static-1 hazard ki definition?

Output ko 1 rehna chahiye lekin momentarily 0 ho jaata hai (1→0→1).

Static-0 hazard ki definition?

Output ko 0 rehna chahiye lekin momentarily 1 pe spike ho jaata hai (0→1→0).

Dynamic hazard ki definition?

Output ko ek baar change hona chahiye lekin settle hone se pehle 3 ya zyada baar change ho jaata hai (jaise 0→1→0→1); ≥3 unequal-delay reconvergent paths chahiye.

K-map par static-1 hazard kaise detect karte hain?

Do adjacent 1-cells dhundho jo alag prime implicants se covered hain jinka koi single implicant dono ko cover nahi karta — ek handoff point.

SOP mein static-1 hazard kaise fix karte hain?

Redundant consensus product term add karo jo adjacent 1s ko cover kare (jaise AB+B'C mein AC add karo).

AB aur B'C ka Consensus?

AC (woh variable drop karo jo ek term mein complemented aur doosre mein true hai).

POS mein static-0 hazard kaise fix karte hain?

Adjacent 0-cells ko cover karne wala consensus sum factor add karo (jaise (A+B)(B'+C) mein (A+C) add karo).

Boolean simplification se hazard kyun nahi remove kar sakte?

Kyunki consensus term steady state par logically redundant hai lekin transitions ke dauran essential hai; ise simplify karna glitch wapas le aata hai.

Kya consensus terms dynamic hazards fix kar sakte hain?

Nahi — dynamic hazards ke liye multi-level network ko redesign karna padta hai (ya hazard-free two-level form); ek single consensus term kaafi nahi hai.

Glitches kabhi kabhi matter kyun nahi karte?

Synchronous designs mein, agar outputs ko ek register settle hone ke baad sample kare, toh transient glitches ignore ho jaate hain — lekin async logic, clocks, aur enables ke liye phir bhi matter karte hain.

Recall Feynman: 12-saal ke bacche ko samjhao

Socho do runners ek hi message ek dost ko de rahe hain, lekin ek zyada lambe, tedhe raaste se daud raha hai. Ek split second ke liye dost slow runner se purana message aur fast runner se naya message sunti hai — aur confused ho jaati hai, ek pal ke liye galat jawab deti hai. Phir slow runner aa jaata hai aur sab theek ho jaata hai. Confusion ka woh pal ek hazard hai. Hum isse ek teesra runner add karke fix karte hain jo hamesha sahi message ek seedhe raaste se le jaata hai, toh dost swap ke dauran bhi kabhi confused nahi hoti.

Connections

Karnaugh Maps and Prime Implicants — hazards adjacent cells se padhe jaate hain.
Consensus Theorem and Redundancy — cure ka algebraic basis.
Propagation Delay and Gate Timing — root cause.
Sum of Products and Product of Sums Forms — jahan consensus terms insert karte hain.
Synchronous vs Asynchronous Circuits — jahan glitches matter karte/nahi karte.
Metastability and Setup-Hold Time — related timing pathologies.