Encoders and priority encoders: Worked examples — Hardware deep dive

This page is the exhaustive drill room for Encoders and priority encoders. The parent note gave you the equations. Here we hunt down every kind of input pattern those equations can ever see, and we work each one to death — so that on an exam or a real chip, no case surprises you.

Before we start, let me re-anchor every symbol so this page stands alone.

The scenario matrix

Here is every class of situation a 4-input priority encoder can be handed. If we work one example from each row, we have literally covered all $2^{4} = 16$ input patterns' worth of behaviour, because every pattern falls into exactly one of these classes.

#	Case class	What makes it special	Covered by
A	Single input, low index ( $I_{0}$ )	the "index 0" trap — needs $V$ to be meaningful	Example 1
B	Single input, high index ( $I_{3}$ )	the winner is also the highest — no suppression	Example 2
C	Two inputs, no conflict on bits	multiple on, but the higher one's code is clean	Example 3
D	Two inputs, suppression fires ( $I_{1}$ & $I_{2}$ )	the $\overline{I_{2}}$ term must kill $I_{1}$	Example 4
E	All four inputs HIGH	maximum contention — top dog $I_{3}$ must win alone	Example 5
F	Zero / degenerate — nothing on	ambiguity with $I_{0}$ ; $V$ saves us	Example 6
G	Real-world word problem	interrupt lines firing together	Example 7
H	Exam-style twist — plain vs priority	same input, two devices, different answers	Example 8

Figure 1 shows the whole priority-encoder as a little "tournament bracket" so you can see what "highest index wins" means.

Look at the bracket: each input enters at the bottom, and whenever a higher-numbered input is on, it eats the lower ones on its way up. Only the survivor's index reaches the output.

Fully worked examples

Example 1 — Case A: the lonely low input

Example 2 — Case B: the lonely high input

Example 3 — Case C: two on, no bit conflict

Example 4 — Case D: suppression must fire

In Figure 2, the red arrow is $I_{2}$ vetoing $I_{1}$ 's attempt to set $Y_{0}$ . That crossed-out path is exactly $\overline{I_{2}} = 0$ .

Example 5 — Case E: everybody on at once

Example 6 — Case F: the empty row (degenerate)

Example 7 — Case G: real-world interrupt lines

Worked example Statement

An interrupt controller wires four devices to $I_{0} .. I_{3}$ : timer= $I_{0}$ , keyboard= $I_{1}$ , disk= $I_{2}$ , network= $I_{3}$ . Suddenly the keyboard and the disk both raise a request: $I_{1} = 1$ , $I_{2} = 1$ , others $0$ . Which device does the CPU service, and what code goes on the bus?

Forecast: Two devices scream at once. Which "wins" the CPU's attention?

Map to inputs: $(I_{3}, I_{2}, I_{1}, I_{0}) = (0, 1, 1, 0)$ . Why? Translate the words into wire states.
$V = 0 + 1 + 1 + 0 = 1$ . Why? There is a real request pending, so the CPU should interrupt.
$Y_{1} = I_{2} + I_{3} = 1 + 0 = 1$ . Why? Disk is index 2, bit-1 set.
$Y_{0} = I_{3} + I_{1} \overline{I_{2}} = 0 + 1 \cdot 0 = 0$ . Why? The disk ( $I_{2}$ ) vetoes the keyboard ( $I_{1}$ ) — disk has higher priority.
Output $= 10 = 2 \Rightarrow$ service the disk first; the keyboard request stays pending for next cycle.

Verify: Highest-priority active device is the disk (index 2), code $10$ . ✅ This is why real interrupt hardware uses priority encoders — deterministic "serve the most urgent" behaviour, exactly as in Example 4's arithmetic.

Example 8 — Case H: exam twist, plain vs priority on the SAME input

Worked example Statement

Given $I_{2} = 1$ and $I_{1} = 1$ (others 0), feed it into (a) a plain 4-to-2 encoder and (b) a priority encoder. Show the two answers differ, and explain which is "correct".

Recall the plain equations (no suppression, no $V$ ): $Y_{0}^{plain} = I_{1} + I_{3}, Y_{1}^{plain} = I_{2} + I_{3} .$

Forecast: Will the two devices agree? Predict both outputs.

Plain $Y_{0} = I_{1} + I_{3} = 1 + 0 = 1$ ; plain $Y_{1} = I_{2} + I_{3} = 1 + 0 = 1$ . Why? The plain encoder blindly ORs. It sees a bit-0 vote ( $I_{1}$ ) and a bit-1 vote ( $I_{2}$ ) and lights both.
Plain output $= 11 = 3$ . Why wrong? No input 3 is on. OR merged bits from indices 1 and 2 into a phantom index 3.
Priority (from Example 4): $Y_{1} = 1$ , $Y_{0} = 0 \Rightarrow 10 = 2$ , $V = 1$ . Why right? Suppression kept only the highest index (2).
Compare: plain says $3$ (nonsense), priority says $2$ (the disk/highest input).

Verify: Plain gives $3$ , priority gives $2$ ; they disagree by exactly the $\overline{I_{2}}$ suppression on $Y_{0}$ . ✅ Figure 3 lays the two truth-behaviours side by side.

Figure 3: the yellow bar (plain) jumps to $3$ for the two-input case, while the green bar (priority) correctly caps at $2$ . The gap between them is the suppression term.

Coverage check — did we hit every cell?

Recall Did every matrix row get an example?

A → Ex 1 · B → Ex 2 · C → Ex 3 · D → Ex 4 · E → Ex 5 · F → Ex 6 · G → Ex 7 · H → Ex 8. Every class covered. ::: Yes — all 8 rows, spanning single/multiple/all/none inputs plus a word problem and an exam contrast.

Quick self-test:

Two inputs

I_{1} = 1, I_{3} = 1

into the priority encoder — output?

Y_{1} = 1, Y_{0} = 1 \Rightarrow 11 = 3

(Case C logic:

I_{3}

outranks

I_{1}

All zeros — what tells you the

00

is meaningless?

The valid bit

V = 0

(Case F).

Which single example proves the

\overline{I_{2}}

term is necessary?

Example 4 (

I_{2}

and

I_{1}

both on) — without it

Y_{0}

would wrongly be

1

Connections

Parent topic — the equations drilled here.
Interrupt controllers — Example 7 is a live use of the priority rule.
Karnaugh maps — the tool that derives the suppression term from the don't-care truth table.
Boolean algebra simplification — justifies $I_{3} + I_{1} \overline{I_{2}}$ as the minimal $Y_{0}$ .
Decoders · Multiplexers · Combinational circuits — surrounding topics.