Reverse bias behavior: Worked examples — Hardware deep dive

This page is a drill sheet. The parent note built the theory; here we hit every kind of question reverse bias can throw at you — every sign of voltage, every extreme temperature, the zero-input case, the limiting cases, a real-world leakage problem, and an exam twist. Work each one yourself first (that's what "Forecast:" is for), then read the steps.

Everything you need from the parent, restated in one place:

The scenario matrix

Every reverse-bias question lands in one of these cells. The examples below are tagged with the cell they cover.

Cell	What varies	Question type	Example
A. $V = 0$	zero input	What is $I$ with no bias?	Ex 1
B. small reverse $∣ V ∣ \sim V_{T}$	sign flip near zero	Is the " $- I_{S}$ " shortcut valid yet?	Ex 2
C. large reverse $∣ V ∣ ≫ V_{T}$	limiting value	Does more voltage give more current?	Ex 3
D. two reverse voltages	saturation / independence	Compare $∣ I ∣$ at $- 2$ V vs $- 10$ V	Ex 4
E. temperature up/down	$I_{S}$ scaling	Leakage at hot & cold	Ex 5
F. depletion geometry	$V_{bi} - V$ law	Width & capacitance vs $V$	Ex 6 (figure)
G. real-world word problem	apply to leakage budget	Will a sensor drift?	Ex 7
H. exam twist / breakdown	which mechanism, temp sign	Identify Zener vs avalanche	Ex 8

Worked examples

Worked example 2 — Cell B: small reverse bias, is "

$- I_{S}$ " already valid? Same diode. Find $I$ at $V = - 0.026 V$ (about one $V_{T}$ of reverse bias), and compare to the shortcut $- I_{S}$ .

Forecast: At only one thermal voltage, is the exponential already negligible, or does it still matter?

Exponent: $V / (n V_{T}) = - 0.026/0.02585 \approx - 1.006$ . Why this step? We need the actual ratio, not the shortcut, because $∣ V ∣$ is not $≫ V_{T}$ yet.
$e^{- 1.006} \approx 0.3657$ . Why this step? This is the term the shortcut throws away — here it is still 37% of 1, so we must keep it.
$I = 10 nA (0.3657 - 1) = 10 nA \times (- 0.6343) \approx - 6.34 nA$ . Why this step? Only one $V_{T}$ of reverse bias, so the diode is not fully saturated — the true magnitude ( $6.34$ nA) is well below $I_{S}$ .

Verify: The shortcut $- I_{S} = - 10 nA$ would be wrong by $37%$ here. Lesson: $- I_{S}$ is only safe once $∣ V ∣ ≫ V_{T}$ . ✓

Worked example 5 — Cell E: temperature up

and down (leakage scaling) $I_{S} = 10 nA$ at $25^{\circ} C$ . Find the reverse leakage at $85^{\circ} C$ (a hot car dashboard) and at $- 5^{\circ} C$ (a cold morning).

Forecast: Which changes leakage more — heating by $60^{\circ}$ or cooling by $30^{\circ}$ ?

Hot case: $Δ T = 85 - 25 = 60^{\circ} C = 6$ steps of $10^{\circ}$ . Multiply by $2^{6} = 64$ . Why this step? The rule "doubles per $10^{\circ} C$ " comes from $I_{S} \propto n_{i}^{2} \propto e^{- E_{g} / k T}$ ; each $10^{\circ}$ multiplies by ~2.
$I_{S} (85^{\circ} C) \approx 10 nA \times 64 = 640 nA$ .
Cold case: $Δ T = - 5 - 25 = - 30^{\circ} C = - 3$ steps. Multiply by $2^{- 3} = 1/8$ . Why this step? Cooling removes thermal generation, so leakage shrinks — same rule, negative exponent.
$I_{S} (- 5^{\circ} C) \approx 10 nA \times \frac{1}{8} = 1.25 nA$ .

Verify: Hot leakage went up 64×, cold went down 8×. Heating dominates because it is exponential and we heated by more steps. Units stay nA throughout. ✓

Worked example 6 — Cell F: depletion width & capacitance vs voltage (geometry)

A junction has $W_{0} = 0.5 μ m$ and $C_{j 0} = 2 pF$ at $V = 0$ , with $V_{bi} = 0.7 V$ . Find $W$ and $C_{j}$ at $V = - 6.3 V$ .

Forecast: The total voltage across the junction goes from $0.7$ V to $0.7 + 6.3 = 7$ V — a 10× jump. Does $W$ grow 10×?

Compute the ratio $\frac{V _{bi} - V}{V _{bi}} = \frac{0.7 - ( - 6.3 )}{0.7} = \frac{7}{0.7} = 10$ . Why this step? Reverse bias ( $V < 0$ ) adds to the built-in voltage, so the charge-supporting voltage is $V_{bi} - V$ . Look at the widening shaded band in the figure.
Width: $W = W_{0} 10 = 0.5 μ m \times 3.162 \approx 1.58 μ m$ . Why this step? Charge grows $\propto W$ but the voltage it supports grows $\propto W^{2}$ (integrate Poisson twice), so $W \propto voltage$ — that's why 10× voltage gives only $10 \approx 3.16 \times$ width.
Capacitance: $C_{j} = C_{j 0} / 10 = 2 pF /3.162 \approx 0.632 pF$ . Why this step? $C_{j} = ε A / W$ — a wider "capacitor gap" means less capacitance. This is exactly the varactor effect: tune voltage to tune capacitance.

Verify: $W \times C_{j} = 1.58 μ m \times 0.632 pF = 0.5 \times 2 = 1.0$ (product $W_{0} C_{j 0}$ is constant since $C_{j} \propto 1/ W$ ). Both moved by the same factor $10$ . ✓

Worked example 7 — Cell G: real-world word problem (leakage budget)

A photodiode circuit tolerates at most $200 nA$ of dark (reverse) leakage. The diode has $I_{S} = 5 nA$ at $25^{\circ} C$ and runs reverse-biased at $- 3 V$ . Up to what temperature can the circuit stay within budget?

Forecast: Will it survive a hot $75^{\circ} C$ enclosure?

At $- 3$ V, $∣ V ∣ ≫ V_{T}$ , so $∣ I ∣ \approx I_{S}$ (saturation). The voltage plays no role in the budget. Why this step? By Cell C/D logic, only $I_{S}$ matters — the leakage is purely thermal.
Budget hit when $I_{S} (T) = 200 nA = 5 nA \times 2^{Δ T /10}$ , so $2^{Δ T /10} = 40$ . Why this step? Set the temperature-scaled leakage equal to the ceiling and solve for the rise.
$Δ T /10 = lo g_{2} 40 = 5.32$ , so $Δ T = 53.2^{\circ} C$ . Why this step? Undo the doubling with a base-2 log to find how many $10^{\circ}$ steps fit.
Max temperature $= 25 + 53.2 = 78.2^{\circ} C$ .

Verify: At $75^{\circ} C$ ( $Δ T = 50$ ): $I_{S} = 5 nA \times 2^{5} = 160 nA < 200 nA$ — safe. ✓ So yes, it survives the $75^{\circ}$ enclosure, with $\sim 3^{\circ}$ of margin.

Worked example 8 — Cell H: exam twist (identify the breakdown)

Two silicon diodes break down: Diode X at $3.9 V$ and, when heated, its $V_{B R}$ drops to $3.8 V$ . Diode Y at $12 V$ and, when heated, its $V_{B R}$ rises to $12.3 V$ . Name each mechanism.

Forecast: Guess before reading the rule — which one is tunneling?

Diode X: low voltage ( $≲ 5 V$ ) and negative temperature coefficient ⇒ Zener (tunneling). Why this step? Heating stretches the lattice and shrinks the bandgap, making tunneling easier, so $V_{B R}$ falls — the signature of Zener breakdown. Low voltage means a heavily doped, thin depletion region where the field can tear electrons straight out of bonds.
Diode Y: high voltage ( $≳ 6 V$ ) and positive temperature coefficient ⇒ avalanche (impact ionization). Why this step? Heating increases lattice vibrations that scatter carriers before they gain enough energy to knock loose others, so you need more voltage — $V_{B R}$ rises. That is the fingerprint of the avalanche chain reaction.

Verify: Consistent with the parent's two-mechanism table: low-V + negative temp coeff = Zener; high-V + positive temp coeff = avalanche. ✓

Recall Predict BEFORE checking (matrix self-test)

Which cell does each of these belong to? Doubling temperature effect on leakage ::: Cell E (temperature scaling of $I_{S}$ ). " $I$ at $- 10$ V equals $I$ at $- 2$ V" ::: Cell D (saturation / voltage independence). " $W$ grows only $10$ when voltage grows 10×" ::: Cell F (depletion geometry, $V_{bi} - V$ law). " $V_{B R}$ falls with heat at 3.9 V" ::: Cell H (Zener breakdown identification).

Connections

Reverse bias behavior — parent topic these drills belong to
Shockley diode equation — the current tool used in Cells A–D
Depletion region & built-in potential — the width/capacitance tool for Cell F
Varactor diodes — the application behind Cell F
Zener diodes — the breakdown physics behind Cell H
Doping concentration N_A N_D — sets $I_{S}$ and the depletion width
Forward bias behavior — the mirror case for contrast