Built-in potential of a junction: Worked examples — Hardware deep dive

This page is the exercise gym for the parent note. There you learned why a voltage appears and how to derive $V_{bi} = \frac{k T}{q} ln (\frac{N _{A} N _{D}}{n _{i}^{2}}) .$ Here we hit that formula from every angle it can be attacked from in a homework or exam — every sign of the log, every degenerate input, both temperature and material changes, and the sneaky "voltmeter" trap.

Intuition Before we compute anything, name every symbol once more

$k T / q$ is the thermal voltage $V_{T}$ : a voltage that measures how much "push" random thermal jiggling gives carriers. At room temperature ( $T = 300$ K) it is $0.02585$ V $= 25.85$ mV. Picture it as the natural "voltage unit" of a warm semiconductor.
$N_{A}$ (acceptors, p-side) and $N_{D}$ (donors, n-side) are how many dopant atoms per cubic centimetre the factory put in. Bigger number = more crowded with one carrier type.
$n_{i}$ is the intrinsic carrier concentration — how many electron–hole pairs a pure crystal makes by itself from heat alone. See Intrinsic carrier concentration.
$ln$ is the natural logarithm: it answers "e to what power gives this number?" We use it (not a plain ratio) because it fell out of integrating $\int d n / n$ in the parent derivation — the log is what you get when the rate of change of something is proportional to the thing itself.

The scenario matrix

Every problem this formula can throw at you is one of these cells. The examples below are tagged with the cell they cover.

Cell	What varies / what's tested	Sign of the log argument	Covered by
A	Ordinary asymmetric Si junction	$\frac{N _{A} N _{D}}{n _{i}^{2}} ≫ 1$ → $V_{bi} > 0$	Ex 1
B	Symmetric doping ( $N_{A} = N_{D}$ )	$> 0$	Ex 2
C	Change doping 10× (log sensitivity)	$> 0$ , small shift	Ex 3
D	Different material (Ge, big $n_{i}$ )	ratio smaller → smaller $V_{bi}$	Ex 4
E	Temperature change ( $n_{i}$ grows)	ratio shrinks → $V_{bi}$ falls	Ex 5
F	Degenerate / limiting: doping → $n_{i}$	argument → $1$ , so $V_{bi} \to 0$	Ex 6
G	"Below intrinsic" pathological input	argument $< 1$ → $ln < 0$ → $V_{bi} < 0$	Ex 7
H	Word problem + voltmeter twist	— (conceptual)	Ex 8
I	Reverse-engineer doping from $V_{bi}$	invert the log	Ex 9

We'll walk A → I in order.

Cell A — the ordinary asymmetric junction

Worked example Example 1 (Cell A)

Silicon, $T = 300$ K: $N_{A} = 1 0^{17} cm^{- 3}$ , $N_{D} = 1 0^{16} cm^{- 3}$ , $n_{i} = 1.0 \times 1 0^{10} cm^{- 3}$ . Find $V_{bi}$ .

Forecast: Silicon diodes "turn on" near 0.7 V. Guess: somewhere between 0.7 and 0.8 V.

Form the argument $\frac{N _{A} N _{D}}{n _{i}^{2}} = \frac{1 0 ^{17} \cdot 1 0 ^{16}}{( 1 0 ^{10} ) ^{2}} = \frac{1 0 ^{33}}{1 0 ^{20}} = 1 0^{13}$ . Why this step? The formula's inside is a pure ratio of concentrations; grouping powers of ten first keeps the arithmetic clean.
Take the natural log: $ln (1 0^{13}) = 13 ln 10 = 13 \times 2.302585 = 29.93$ . Why this step? $ln$ answers "e-to-what-power," and $ln (1 0^{13}) = 13 ln 10$ turns a huge number into a small one — that's exactly why doping has weak control (see Ex 3).
Multiply by thermal voltage: $V_{bi} = 0.02585 \times 29.93 = 0.7738 V$ . Why this step? $V_{T}$ converts the dimensionless log into volts.

Verify: $0.774$ V sits inside the textbook 0.6–0.8 V band for silicon ✓. Units: volts × (dimensionless) = volts ✓.

Cell B — symmetric doping

Cell C — the log-sensitivity test

Figure — Built-in potential of a junction

Look at the chalk-blue curve above: it's $V_{bi}$ versus the log of doping. Because the horizontal axis is already logarithmic, the curve is a straight line — each tenfold hop rightward climbs the same tiny 60 mV. That flat slope is the reason you can never dope your way to a huge built-in potential.

Cell D — a different material (germanium)

Cell E — the temperature scenario

Worked example Example 5 (Cell E)

Silicon from Ex 1, but heated from 300 K to 350 K. Two things change: $V_{T} = k T / q$ rises, and $n_{i}$ rises fast ( $n_{i} \propto T^{3/2} e^{- E_{g} /2 k T}$ ). Does $V_{bi}$ go up or down?

Forecast: The prefactor $V_{T}$ rising helps $V_{bi}$ ; the exploding $n_{i}$ hurts it. Silicon empirically falls ~2 mV/°C, so bet on a decrease.

New thermal voltage: $V_{T} = \frac{k T}{q} \propto T$ , so $V_{T} (350) = 0.02585 \times \frac{350}{300} = 0.03016$ V.
New $n_{i}$ . Using $E_{g} = 1.12$ eV for Si and Boltzmann constant $k = 8.617 \times 1 0^{- 5}$ eV/K, the ratio is $\frac{n _{i} ( 350 )}{n _{i} ( 300 )} = (\frac{350}{300})^{3/2} exp [- \frac{E _{g}}{2 k} (\frac{1}{350} - \frac{1}{300})] .$ Numerically the exponent is $- \frac{1.12}{2 ( 8.617 \times 1 0 ^{- 5} )} (\frac{1}{350} - \frac{1}{300}) = + 3.093$ , and $(350/300)^{1.5} = 1.260$ , giving a factor $1.260 e^{3.093} = 27.71$ . So $n_{i} (350) = 2.771 \times 1 0^{11}$ . Why this step? $n_{i}$ is the term that swings hardest with temperature; ignoring it is the classic mistake.
New argument $= \frac{1 0 ^{33}}{( 2.771 \times 1 0 ^{11} ) ^{2}} = \frac{1 0 ^{33}}{7.68 \times 1 0 ^{22}} = 1.302 \times 1 0^{10}$ .
New $V_{bi}$ $= 0.03016 \times ln (1.302 \times 1 0^{10}) = 0.03016 \times 23.29 = 0.7025 V$ .

Verify: $V_{bi}$ dropped from $0.774$ to $0.702$ V, i.e. $- 0.071$ V over $50^{\circ}$ C $= - 1.4$ mV/°C by this simple model — same sign and order of magnitude as the textbook ~ $- 2$ mV/°C ✓. The rising $V_{T}$ did not win: the shrinking log dominates. See Energy band diagrams for the band-gap picture behind $E_{g}$ .

Cell F — the limiting case: doping approaches intrinsic

Cell G — the pathological input (argument below 1)

Worked example Example 7 (Cell G — "what CAN'T happen and why")

A student writes $N_{A} = N_{D} = 1 0^{8} cm^{- 3}$ (below silicon's $n_{i} = 1 0^{10}$ ). What does the formula spit out, and is it physical?

Forecast: Doping below intrinsic is nonsense (you can't have fewer carriers than the pure crystal), but let's see what the math says and what warning sign it gives.

Argument $= \frac{( 1 0 ^{8} ) ^{2}}{( 1 0 ^{10} ) ^{2}} = \frac{1 0 ^{16}}{1 0 ^{20}} = 1 0^{- 4}$ . Why this step? Now the numerator is smaller than $n_{i}^{2}$ , so the ratio drops below 1.
Log of a number below 1 is negative: $ln (1 0^{- 4}) = - 4 \times 2.302585 = - 9.21$ . Why this step? $ln$ crosses zero at 1 and goes negative for inputs in $(0, 1)$ — this is the sign flip the matrix warned about.
Volts $= 0.02585 \times (- 9.21) = - 0.238 V$ .

Verify: The formula yields a negative $V_{bi}$ ✓ — a mathematical red flag. Physically, the fully-ionized approximation ( $n_{n} \approx N_{D}$ ) breaks once doping $≲ n_{i}$ : the majority carrier is then set by $n_{i}$ , not $N_{D}$ . So the correct physical answer is still $V_{bi} \approx 0$ (as in Ex 6), and a negative output tells you the model's assumptions were violated, not that a "reverse" junction formed.

Cell H — the word problem + voltmeter twist

Worked example Example 8 (Cell H)

A friend builds the Ex 1 diode ( $V_{bi} = 0.774$ V), clips a voltmeter across it, and expects a free 0.774 V battery. The meter reads 0.000 V. Explain, and state what current flows.

Forecast: We know from the parent note this is the "free energy" trap. Guess: contact potentials cancel it, current = 0.

Identify every junction in the loop. The probe adds a metal–p contact and a metal–n contact. Each contact has its own contact potential. Why this step? A voltmeter never touches the depletion region directly; it always inserts extra junctions.
Sum potentials around the closed loop (Kirchhoff's voltage law). The two metal–semiconductor contact potentials add up to $- V_{bi}$ exactly, so the total is $V_{bi} + (contacts) = 0$ . Why this step? At thermal equilibrium the Fermi level is flat everywhere; a flat Fermi level means zero net potential difference between the two metal leads.
Current $= 0$ because there is no net EMF and no external source.

Verify: Meter reads $0$ V, current $= 0$ ✓. $V_{bi}$ is an internal equilibrium quantity — real across the depletion layer, invisible at the terminals. The moment you apply an external battery you leave equilibrium and enter diode I–V territory.

Cell I — reverse-engineering doping from a measured $V_{bi}$

Worked example Example 9 (Cell I)

A capacitance–voltage measurement gives $V_{bi} = 0.65$ V for a silicon junction with known $N_{D} = 1 0^{15} cm^{- 3}$ . Find the p-side doping $N_{A}$ . ( $n_{i} = 1 0^{10}$ , $V_{T} = 0.02585$ .)

Forecast: 0.65 V is a bit below the symmetric- $1 0^{16}$ value (0.714 V), and $N_{D}$ here is lower ( $1 0^{15}$ ), so $N_{A}$ must be moderate — guess somewhere near $1 0^{16}$ .

Isolate the log: divide by $V_{T}$ : $\frac{V _{bi}}{V _{T}} = \frac{0.65}{0.02585} = 25.145$ . Why this step? We're inverting the formula, so first strip off the prefactor.
Undo the log (exponentiate): $\frac{N _{A} N _{D}}{n _{i}^{2}} = e^{25.145} = 8.36 \times 1 0^{10}$ . Why this step? $e^{(\cdot)}$ is the exact opposite of $ln$ ; applying it recovers the ratio.
Solve for $N_{A}$ : $N_{A} = \frac{8.36 \times 1 0 ^{10} \cdot n _{i}^{2}}{N _{D}} = \frac{8.36 \times 1 0 ^{10} \times 1 0 ^{20}}{1 0 ^{15}} = 8.36 \times 1 0^{15} cm^{- 3}$ . Why this step? Multiply through by $n_{i}^{2}$ and divide by the known $N_{D}$ .

Verify: Plug back: $\frac{8.36 \times 1 0 ^{15} \cdot 1 0 ^{15}}{1 0 ^{20}} = 8.36 \times 1 0^{10}$ ; $ln (8.36 \times 1 0^{10}) = 25.15$ ; $\times 0.02585 = 0.650$ V ✓. $N_{A} \approx 8.4 \times 1 0^{15}$ sits right in the "moderate" range we forecast.

Recall Quick self-test

A Si junction reads $V_{bi} = 0.834$ V. Roughly what changed versus the 0.774 V baseline of Ex 1? ::: The doping product went up ~10× (each factor of 10 adds ~60 mV; $0.834 - 0.774 = 0.060$ V). If you heat a diode, does $V_{bi}$ rise or fall, and which term wins? ::: It falls; the fast-growing $n_{i}$ shrinks the log faster than the rising $V_{T}$ prefactor lifts it. What is $ln (1)$ and why does it set the "no built-in potential" floor? ::: $ln (1) = 0$ ; when doping equals $n_{i}$ there is no concentration contrast, so $V_{bi} = 0$ .

Connections

Built-in potential of a junction — parent
Depletion region width, Einstein relation, Mass-action law, Intrinsic carrier concentration, Energy band diagrams, PN junction under bias, Diode I-V equation