Interrupts — ISR design, NVIC priority, interrupt latency: Exercises

5.5.7 · D4 · Coding › Embedded Systems & Real-Time Software › Interrupts — ISR design, NVIC priority, interrupt latency

Problem. Har phrase ke liye parent note se term batao: (a) "hardware automatically 8 registers save karta hai tumhara code chalane se pehle," (b) "ISR addresses ka array jisme hardware index karta hai," (c) "wo peripheral jo decide karta hai kaun sa interrupt chalega aur kis priority par."

Recall Solution (L1.1)

(a) Stacking — CPU auto-push karta hai $R 0$ – $R 3$ , $R 12$ , $L R$ (link register, return address), $P C$ (program counter, aage kya chalta hai), aur $x P S R$ (upar define kiya gaya Program Status Register) — kul 8 words — stack par. "For free" kyun? Kyunki ye caller-saved hain, tumhara ISR (Interrupt Service Routine) ek plain C function ho sakta hai. (b) Vector table — ISR start addresses ka ek array; NVIC interrupt number ko index ki tarah use karta hai. (c) NVIC (Nested Vectored Interrupt Controller).

L1.2 — Kaun sa number jeetta hai?

Problem. Do interrupts pending hain: IRQ-X ki priority number $2$ hai, IRQ-Y ki priority number $5$ hai. Cortex-M par kaun zyada urgent hai?

Recall Solution (L1.2)

IRQ-X (number $2$ ). Kyun? Cortex-M par, ==lower numeric value = higher urgency==; priority $0$ sabse urgent hoti hai. Ye rozmarra ki "level 10 beats level 1" wali soch ka ulta hai — neeche L1 mistake dekho.

Level 2 — Application

L2.1 — Cycles ko time mein convert karo

Problem. Ek Cortex-M4 $48$ MHz par chalta hai. Deterministic hardware interrupt entry ka cost $12$ cycles hai. Ise nanoseconds mein convert karo.

Recall Solution (L2.1)

Ek cycle: $t_{cyc} = 1/ (48 \times 1 0^{6}) = 2.0833 \times 1 0^{- 8} s \approx 20.83 ns$ . $t_{hw} = 12 \times 20.83 ns = 250 ns$ Multiply kyun karte hain? Latency count karta hai kitne clock ticks guzre, aur har tick $t_{cyc}$ last karta hai; total time hai (count) × (time per tick).

L2.2 — Priority-level counting

Problem. Ek chip $N = 3$ priority bits implement karta hai. PRIGROUP $p = 2$ bits preemption ko assign karta hai. Kitne preemption levels aur kitne sub-priority levels hain? Total verify karo.

Formula Counting rule — yahan scratch se derive kiya gaya

Hume count karna hai kitne distinct values ek group of bits hold kar sakta hai. Key fact: $k$ binary bits exactly $2^{k}$ distinct patterns hold kar sakte hain (bit 1 bit 0 ka count double karta hai, bit 2 phir double karta hai, … toh $2 \times 2 \times \dots = 2^{k}$ ).

Preemption field mein $p$ bits hain → ye $2^{p}$ distinct values hold kar sakta hai → $preempt levels = 2^{p}$ .
Sub field mein baaki $N - p$ bits hain → ye $2^{N - p}$ distinct values hold kar sakta hai → $sub levels = 2^{N - p}$ . $preempt levels = 2^{p}, sub levels = 2^{N - p}$ Consistency check: har distinct priority ek (preempt, sub) pair hai, toh total $= 2^{p} \cdot 2^{N - p} = 2^{p + (N - p)} = 2^{N}$ — exactly wo number jo $N$ implemented bits hold kar sakte hain. Split line boundary move karta hai lekin kabhi levels create ya destroy nahi karta.

Recall Solution (L2.2)

Upar derive kiye rule ka use karte hue, $preempt = 2^{p}$ aur $sub = 2^{N - p}$ , $N = 3$ , $p = 2$ ke saath:

Preempt levels $= 2^{2} = 4$ . Kyun? $2$ bits $4$ distinct groups encode karte hain jo ek doosre ko preempt kar sakte hain.
Sub levels $= 2^{3 - 2} = 2^{1} = 2$ . Kyun? $1$ bacha hua bit $2$ tiebreaker slots encode karta hai.
Total $= 4 \times 2 = 8 = 2^{3} = 2^{N}$ . ✔ Split kabhi levels create ya destroy nahi karta.

L2.3 — Worst-case latency

Problem. CPU $= 80$ MHz. Hardware entry $= 12$ cycles. Tumhara sabse lamba critical section $40$ cycles ke liye interrupts mask karta hai. Worst-case latency nanoseconds mein compute karo.

Recall Solution (L2.3)

Figure — Interrupts — ISR design, NVIC priority, interrupt latency

Upar ka timeline padho: event masked window ke andar fire karta hai, toh "ISR kab start ho sakta hai?" ka clock tab tak hardware entry ke through tick karna shuru nahi kar sakta jab tak mask lift nahi ho jaata. Do red/amber bars end-to-end hain, overlapping nahi.

t_{cyc} = 1/ (80 \times 1 0^{6}) = 12.5 ns

t_{lat,worst} = (12 + 40) \times 12.5 ns = 52 \times 12.5 ns = 650 ns

$40$ kyun add karte hain? Worst case hai event ka thik baad fire karna jab tune interrupts mask kiye — ise hardware stacking shuru hone se pehle poora critical section wait karna padta hai. Critical section ka idea dekho.

Level 3 — Analysis

L3.1 — Kya X, Y ko preempt karta hai?

Problem. Chip mein $N = 4$ bits hain, PRIGROUP → $3$ preempt bits, $1$ sub bit. IRQ-A: preempt $= 1$ , sub $= 1$ . IRQ-B: preempt $= 2$ , sub $= 0$ . IRQ-C: preempt $= 2$ , sub $= 1$ . Jawab do: (a) Kya A, running B ko preempt karta hai? (b) Agar B aur C simultaneously pending hain (koi nahi chal raha abhi), kaun pehle chalta hai, aur kya wo doosre ko preempt karta hai?

Recall Solution (L3.1)

Figure kaise padhen: neeche wala cyan band IRQ-B execute hota hua dikhata hai; jab amber IRQ-A bar aata hai, B ka band pause ho jaata hai (wahan ek gap hai) — ye gap preemption ka visual proof hai. B sirf A ki amber bar khatam hone ke baad resume karta hai. IRQ-C, B ki preemption priority share karta hua, right mein queue mein baitha hai aur kabhi apna overlapping band nahi paata, kyunki wo kisi running peer mein kabhi cut nahi kar sakta. (a) Haan. Preemption sirf preemption priority se decide hoti hai. A ka preempt

= 1

hai, B ka preempt

= 2

; lower number = higher urgency, toh A, B ko mid-execution interrupt kar sakta hai. (b) B pehle chalta hai, aur wo C ko preempt NAHI karta. B aur C same preemption priority (

2

) share karte hain, toh koi bhi doosre ko interrupt nahi kar sakta. Unka sub-priority pending tie break karta hai: B sub

= 0

, C sub

= 1

ko beat karta hai (lower = pehle). Jab B complete ho jaata hai, C chalta hai. Sub-priority kabhi preempt kyun nahi karta: ye sirf queue mein already waiting cheezein order karta hai; ek running ISR ko rokne ki iske paas koi power nahi hai.

L3.2 — Tail-chaining ki bachat

Problem. Do interrupts B phir C back-to-back pending hain. Naive handling: B ke baad unstack ( $\approx 12$ cyc) phir C ke liye re-stack ( $\approx 12$ cyc). Tail-chaining B→C transition ke liye sirf $\approx 6$ cyc cost karta hai. (a) Kitne cycles bachte hain? (b) Unstack+restack skip karna kyun safe hai?

Recall Solution (L3.2)

Figure kaise padhen: upar wali row naive path hai — "B body" ke baad ek wide amber block (unstack

12

+ restack

12

) "C body" shuru hone se pehle burn hota hai. Neeche wali row tail-chaining hai — same "B body" ek narrow amber block (chain

6

) ke through seedha "C body" mein flow karta hai. Do amber blocks ki width ka difference hi bachat hai, jo neeche amber mein call out ki gayi hai. (a) Naive transition cost

= 12 + 12 = 24

cyc. Tail-chained

= 6

cyc. Bachat

= 24 - 6 = 18

cyc. (b) Stack par 8-register saved context B ke return hote hi still valid hai — beech mein ISRs ke bahar kuch nahi chala. Un 8 words ko pop karna sirf immediately identical 8 words push karne ke liye pure wasted work hai, toh hardware seedha B→C jump karta hai, stack frame ko jagah par rakhta hua.

Level 4 — Synthesis

L4.1 — UART receive ISR design karo

Problem. Bytes ek UART par $115200$ baud par aate hain, $10$ bits per byte (start + 8 data + stop). (a) Kitne bytes per second, aur inter-byte time budget µs mein kya hai? (b) ISR ko minimum kya kaam karna chahiye taaki wo budget mein rahe, aur heavy parsing kahan jaayegi?

Recall Solution (L4.1)

(a) Byte rate $= 115200/10 = 11520$ bytes/sec. Time budget per byte $= 1/11520 = 8.68 \times 1 0^{- 5}$ s $= 86.8$ µs. Toh ISR + baaki sab kuch ek byte handle karna complete kar le agle ke aane se pehle. (b) Minimum ISR work: (1) pehle RX interrupt flag clear karo pehle (taaki wo forever re-enter na ho), (2) data register se received byte padho (ye real hardware par flag bhi often clear karta hai), (3) ise ek ring buffer mein push karo, (4) ek volatile "data ready" flag set karo, (5) return karo. Heavy work (protocol parsing, checksums, string handling) main loop mein jaata hai — deferred / bottom-half mein. Split kyun karte hain? Lamba ISR har equal/lower-priority interrupt ki latency badhata hai; ise ek muthi bhar instructions par rakhne se $86.8$ µs budget mein agla byte aur baaki IRQs ke liye kaafi jagah bachti hai.

L4.2 — Teen tasks ke liye priorities choose karo

Problem. Tumhare paas teen interrupt sources hain: ek motor safety-stop line (instantly react karna zaroori), ek $1$ kHz control timer (hard deadline), aur ek UART byte (soft — ring buffer jitter absorb karta hai). Chip mein $N = 4$ bits hain, saare $4$ preemption ke liye use hote hain (PRIGROUP → $4$ preempt bits, $0$ sub bits). Preemption priority numbers assign karo aur justify karo.

Recall Solution (L4.2)

$4$ preempt bits ke saath $2^{4} = 16$ levels hain, numbers $0$ (top) … $15$ .

Motor safety-stop → priority $0$ . Sabse time-critical; sab kuch preempt karna zaroori. Yaad rakho tightest deadline ko highest urgency milti hai.
$1$ kHz control timer → priority $1$ . Hard periodic deadline; UART ko preempt karna zaroori lekin safety stop ke aage yield karna.
UART byte → priority $2$ (ya higher number). Ring buffer jitter tolerate karta hai, toh ye dono ke peeche wait kar sakta hai — iska latency briefly badhna harmless hai. Ye order kyun? Lower number = sabse zyada chillaata hai. Numbers assign karo "late reaction se kitna nuksaan hoga?" ke order mein. Safety > hard timing > buffered I/O.

Level 5 — Mastery

L5.1 — Full latency + throughput audit

Problem. Ek Cortex-M4 $72$ MHz par. Deterministic hardware entry $= 12$ cycles. Worst same-or-higher blocking ek critical section hai jo IRQs $30$ cycles ke liye mask karta hai. ISR body khud $60$ cycles chalti hai. (a) Worst-case latency (event → first ISR instruction) ns mein. (b) Total time CPU lower-priority interrupts ke liye unavailable hai is ISR ki wajah se (entry + body + exit unstack $\approx 12$ cycles), ns mein. (c) Ek event source har $5$ µs mein fire karta hai. Kya system keep up kar sakta hai? Kitne margin se?

Recall Solution (L5.1)

$t_{cyc} = 1/ (72 \times 1 0^{6}) = 1.3889 \times 1 0^{- 8}$ s $\approx 13.89$ ns.

(a) $t_{lat} = (12 + 30) \times t_{cyc} = 42 \times 13.89 ns = 583.3 ns$ . $12 + 30$ kyun? Hardware entry tab tak shuru nahi ho sakti jab tak $30$ -cycle mask lift na ho jaaye; sequential hai, toh add karo.

(b) $t_{busy} = entry + body + exit = 12 + 60 + 12 = 84$ cycles $= 84 \times 13.89 ns = 1166.7 ns \approx 1.17$ µs. Teeno kyun sum karte hain? Jis moment hardware entry shuru hoti hai us moment se jab tak ISR fully return kar le, CPU is ISR chal raha hai aur koi lower-priority cheez start nahi ho sakti — toh blocking window jo ek lower-priority interrupt dekhta hai poora contiguous span hai: $12$ -cycle entry (stacking + vector fetch), phir $60$ -cycle body, phir $12$ -cycle exit (unstacking). Ye back-to-back hote hain koi gap nahi, toh teeno add karte hain; koi overlap subtract karne ke liye nahi hai.

(c) Pehle poora firing-to-done span compute karo — event fire hone se lekar ISR completely finish hone tak — kyunki wahi total work hai jo ek event generate karta hai. Ye blocked mask plus busy window hai: $t_{done} = t_{blocked} + entry + body + exit = (30 + 12 + 60 + 12) \times t_{cyc} = 114 \times 13.89 ns = 1583.3 ns \approx 1.58$ µs. $5$ µs se compare kyun karte hain? Agar ek event ka total work ( $1.58$ µs) agla event aane ( $5$ µs baad) se pehle khatam ho jaaye, toh system kabhi peeche nahi padta — har event fully service hota hai time bacha ke. Kyunki $1.58 µs < 5 µs$ , ye keep up karta hai. Margin $= 5 - 1.583 = 3.417$ µs idle time per period. Busy fraction $= 1.583/5 \approx 31.7%$ , main loop aur baaki IRQs ke liye $68%$ headroom bacha ke. Headroom kyun matter karta hai: agar busy fraction $100%$ ke qareeb jaata, toh baaki sab ke liye koi cycles nahi bachte aur deadlines slip karne lagti.

L5.2 — Frozen loop debug karo

Problem. Ye code forever spin karta hai even though ek ISR done = 1 set karta hai. Bug aur fix explain karo, is terms mein ki compiler ne kya kiya.

int done = 0;
// ISR: done = 1;
while (!done) { /* wait */ }

Recall Solution (L5.2)

Bug: done volatile nahi hai. Optimizing compiler dekhta hai ki while loop kabhi done change nahi karta, toh wo done ko RAM se ek register mein ek baar padhta hai, phir cached register value par forever loop karta hai. Ise koi knowledge nahi hai ki ek asynchronous ISR RAM likhta hai. Fix: volatile int done = 0;. Ye kaise kaam karta hai: volatile compiler ko force karta hai ki done ko memory se har loop iteration par re-read kare, toh wo eventually ISR ki write dekh leta hai. Ye classic ISR↔main shared-variable hazard hai. Multi-byte shared data ke liye tum bhi atomic access chahte ho (read/write ke around IRQs mask karo) taaki tum kabhi half-updated value na dekho.

Recall Quick self-test

Lower priority number matlab ::: zyada urgent (0 sabse top hai). Sub-priority ek running equal-preemption ISR ko preempt kar sakta hai? ::: Nahi — ye sirf pending ties break karta hai. ISR ko apna flag early clear kyun karna chahiye? ::: Warna ye forever re-enter ho sakta hai. ISR-shared variables volatile kyun hone chahiye? ::: Taaki compiler unhe register mein cache karne ki bajaye memory se re-read kare. Worst-case latency blocked time aur hardware entry add karta hai — max ya sum? ::: Sum (ye sequential hain).

Exercises — Interrupts — ISR design, NVIC priority, interrupt latency

Level 1 — Recognition

L1.1 — Vocabulary match