CAN bus — frame format, arbitration, error handling — critical in aerospace: Worked examples

5.5.6 · D3 · Coding › Embedded Systems & Real-Time Software › CAN bus — frame format, arbitration, error handling — critic

Is page mein CAN bus ko force karke har tarah ki situation se guzara gaya hai jo bus produce kar sakti hai: arbitration ties, dono directions mein arbitration losses, degenerate one-node cases, error-counter arithmetic har threshold ke paas, ACK collective, aur ek real aerospace word problem. Har ek ko pencil se solve karo reading se pehle.

Saari definitions ke liye parent dekho: CAN bus parent note.

Kuch bhi shuru karne se pehle, woh EK electrical rule yaad karo jis par neeche sab kuch tika hai — wired-AND on an open-collector bus:

Recall Woh single rule jo sab kuch decide karta hai

CAN ka ek bit ya toh dominant (logic 0) hota hai ya recessive (logic 1). Wire AND dikhata hai har us bit ka jo uspe drive kiya gaya ho. Toh ek akela node 0 drive karke poori bus ko 0 force kar deta hai. "Dominant beats recessive." Har example mein yeh dimag ke aage rakho. Agar nodes ek saath 1, 1, 0 drive karein toh bus kya read karega? ::: 0 (dominant wired-AND mein jeet jaata hai)

The scenario matrix

Is topic ki har situation inhi cells mein se kisi ek mein aati hai. Neeche ke examples mein cell(s) label kiye gaye hain.

Cell	Kya vary karta hai	Degenerate / limiting version	Example
A. Arbitration tie then split	do IDs kuch der ke liye agree karte hain, phir differ	pehle hi ID bit par differ karein	Ex 1, Ex 2
B. Direction of loss	kaun sa node back off karta hai (higher-ID loses)	teen nodes, staged elimination	Ex 3
C. Zero / one node	sirf ek talker, ya all-recessive idle	koi transmit nahi karta → bus idle	Ex 4
D. ACK collective	kuch receivers CRC pass karte hain, kuch fail	koi bhi receiver pass nahi karta → ACK error	Ex 5
E. Error counters — success	TEC/REC chadhte hain phir heal hote hain	counter already at 0 negative nahi ja sakta	Ex 6
F. Error counters — thresholds	127, 255 boundaries cross karna	exactly 127 vs 128 par	Ex 7
G. Real-world word problem	IDs urgency se assign karna	fire alarm ko cabin light se beat karna chahiye	Ex 8
H. Exam twist	data length ≠ priority; RTR/extended-ID trap	equal 11-bit ID, different RTR	Ex 9

Ex 1 — Cell A: do IDs jo mid-stream split karte hain

Forecast: winner ko pehle guess karo reading se pehle. (Hint: kaun sa number chhota hai?)

Dono bit strings aligned dekho, MSB (bit 10) left par:

Figure — CAN bus — frame format, arbitration, error handling — critical in aerospace

Step 1 — Bits line up karo aur column by column AND karo. Yeh step kyun? Arbitration bit-by-bit MSB se hoti hai; bus har instant par AND hoti hai un sab bits ka jo dono nodes drive karte hain, isliye hume column by column compare karna hai, decimal numbers nahi.

bit#	9	7	6	4	3	2	1	0
P	1	1	1	0	0	0	0	0
Q	1	1	1	1	0	0	0	0
bus	1	1	1	0	—	—	—	—

Step 2 — Pehla column dhundho jahan woh disagree karte hain. Yeh step kyun? Ek node tabhi lose karta hai jab woh recessive (1) drive kare lekin dominant (0) read kare. Tab tak dono khush hain. Pehla disagreement bit 4 hai: P 0 drive karta hai, Q 1 drive karta hai.

Step 3 — Bit 4 par wired-AND apply karo. Yeh step kyun? Bus = P AND Q = 0 AND 1 = 0. Q ne 1 bheja, 0 read kiya → mismatch → Q back off karta hai aur receiver ban jaata hai. P ko kabhi fight ka pata hi nahi chala aur woh transmit karta raha.

Answer: P jeet jaata hai, Q bit 4 par haarta hai.

Verify: 704 < 720, aur lower ID = higher priority. Winner chhota number hai — consistent. ✓ Yeh bhi: dono IDs pehli baar differ karte hain binary place $2^{4} = 16$ mein, aur $720 - 704 = 16$ . ✓

Ex 2 — Cell A (limiting): woh pehle hi bit par differ karte hain

Forecast: arbitration kitni jaldi decide ho sakti hai?

Step 1 — Pehle bit 10 (the MSB) compare karo. Yeh step kyun? Yeh fastest possible arbitration hai — boundary case. X bit 10 par 0 drive karta hai; Y 1 drive karta hai.

Step 2 — Bit 10 par wired-AND. Bus = 0 AND 1 = 0. Y ne 1 bheja, 0 read kiya → Y turant pehle ID bit par hi haart jaata hai.

Answer: X jeetat hai bit 10 par (arbitration ek bit mein decide).

Verify: 1 < 1024 → X higher priority. ✓ Pehla differing bit ise resolve karta hai; koi bus ek bit se tez decide nahi kar sakti. ✓

Ex 3 — Cell B: teen nodes, staged elimination

Forecast: winner aur elimination ka order guess karo.

Step 1 — Bit 10 par teeno ka AND karo. Yeh step kyun? Bus AND hai sab transmitters ka, sirf do ka nahi. Bit 10 par sab 0 bhejte hain → bus 0 → abhi koi nahi haarta.

Step 2 — Bit 9 tak pahuncho. A 0 bhejta hai, B 0 bhejta hai, C 1 bhejta hai. Bus = 0 AND 0 AND 1 = 0. C ne 1 bheja, 0 read kiya → C bit 9 par eliminate. Yeh step kyun? C ke paas $2^{9} = 512$ place mein 1 hai; A aur B ke paas nahi, isliye C ka bada ID pehle out hota hai.

Step 3 — A aur B continue karte hain. Woh bit 6 tak agree karte hain: A 0 bhejta hai, B 1 bhejta hai. Bus = 0 → B bit 6 par eliminate.

Answer: winner A; elimination order C (bit 9) phir B (bit 6).

Verify: IDs ascending sorted: 256 < 320 < 768 → priority order A > B > C, aur chhota number sabse zyada survive karta hai. ✓ 768 mein bit-9 set hai ( $768 = 512 + 256$ ) → pehle nikla. ✓ 320 mein bit-6 set hai ( $320 = 256 + 64$ ) → bit 6 par nikla. ✓

Ex 4 — Cell C: degenerate cases (ek node, ya koi nahi)

Forecast: kya arbitration ek node ke saath meaningful bhi hai?

Step 1 — Case (a): ek akele driver ka AND. Yeh step kyun? Ek transmitter ke saath, bus = N ka bit har instant par. N hamesha exactly wahi read karta hai jo usne bheja, kabhi mismatch nahi → woh trivially "jeetat hai" aur apna poora frame bhejta hai.

Step 2 — Case (b): sab nodes idle. Yeh step kyun? Ek idle CAN node kuch nahi drive karta, toh har bit float karta hai recessive (1) par. AND of all-1 = 1. Ek idle bus recessive bits ki steady stream read karta hai.

Answer: (a) N hamesha uncontested jeetat hai. (b) idle bus = recessive = logic 1.

Verify: wired-AND of ek input wahi input hai. AND over all-recessive (sab 1s) = 1. ✓ Isliye recovery rule "11 consecutive recessive bits" ko idle bus ka signature maanta hai (dekho Bit stuffing and clock recovery). ✓

Ex 5 — Cell D: ACK collective (aur uski failure)

Forecast: acknowledge karne ke liye kitne receivers chahiye?

Step 1 — Case (a): ACK slot ko kaun overwrite karta hai? Yeh step kyun? Har receiver jisne CRC pass kiya woh ACK slot mein dominant (0) drive karta hai; jo fail kiye woh recessive chhod dete hain. Bus = AND of (recessive T se, 0,0,0 un 3 passers se, 1,1 un 2 failers se) = 0.

Step 2 — T ACK slot read karta hai. T ne recessive bheja, dominant read kiya → "kam se kam ek node ne suna" → frame accepted. Sirf ek dominant kaafi hai.

Step 3 — Case (b): kisi ne pass nahi kiya. Koi receiver dominant nahi drive karta; ACK slot recessive rehta hai. T ne recessive bheja, recessive read kiya → ACK error → T error frame bhejta hai aur retransmit karta hai.

Answer: (a) T dominant (0) read karta hai → success chahe 5 mein se 2 fail ho gaye. (b) all-recessive → ACK error.

Verify: AND(1, 0,0,0, 1,1) = 0 → dominant. ✓ AND(1,1,1,1,1) = 1 → recessive → koi acknowledgement nahi. ✓ CSMA-CD (Ethernet) se compare karo jahan acknowledgement ek alag frame hota hai, collective bit nahi.

Ex 6 — Cell E: error counters chadhte hain phir heal hote hain

Forecast: kya ek witness fast ya slow chadhta hai?

Step 1 — Receiver rule apply karo: har error par REC += 1. Yeh step kyun? Jo node sirf doosron ki errors dekh raha hai use halki saza milti hai (+1), kyunki woh offender nahi hai. 5 errors ke baad: $0 + 5 \times 1 = 5$ .

Step 2 — Success rule apply karo: har successful frame par −1, floor 0 par. Yeh step kyun? Healing slow lekin steady hai. 3 successes ke baad: $5 - 3 = 2$ .

Step 3 — Degenerate floor. Yeh step kyun? Agar R REC = 0 par hota aur successfully receive karta, toh woh 0 rehta — counters kabhi negative nahi jaate (koi "credit" nahi hai).

Answer: REC 2 par khatam hota hai; woh 0 se neeche nahi ja sakta.

Verify: $0 + 5 - 3 = 2$ , aur $max (0, \cdot)$ ise $\geq 0$ rakhta hai. Abhi bhi 127 se kaafi neeche → R Error-Active rehta hai. ✓

Ex 7 — Cell F: 127 aur 255 thresholds cross karna

Forecast: kis error par S Error-Passive ho jaata hai?

Step 1 — Transmitter rule: har error par TEC += 8. Yeh step kyun? Offender ko witness se 8× zyada saza milti hai taaki ek faulty transmitter khud ko jaldi silence kar le (fault confinement). 120 se sequence:

error #	TEC	state (Active if $T E C \leq 127$ , Passive if $> 127$ )
start	120	Error-Active
1	128	Error-Passive ( $128 > 127$ )
2	136	Error-Passive
3	144	Error-Passive
4	152	Error-Passive
5	160	Error-Passive

Step 2 — Boundary subtlety. Yeh step kyun? Threshold hai strictly greater than 127. $T E C = 127$ abhi bhi Active hai; $128$ pehli Passive value hai. Off-by-one traps yahan rehte hain.

Step 3 — TEC = 250 se 255 cross karo. $250 + 8 = 258 > 255 \Rightarrow$ Bus-Off. Yeh step kyun? $T E C > 255$ hard shutdown hai; S khud ko bus se bilkul alag kar leta hai (spec ke anusaar baad mein recoverable — parent mein Mistake 3 dekho).

Answer: S pehle error par Error-Passive ho jaata hai (TEC 128); 250 se, ek error → TEC 258 → Bus-Off.

Verify: $120 + 8 = 128 > 127$ → pehle error par Passive. ✓ $127 \leq 127$ Active hai (boundary). ✓ $250 + 8 = 258 > 255$ → Bus-Off. ✓ (DO-178C / DO-254 aerospace certification ke liye relevant: ek faulty LRU ko khud ko isolate karna chahiye.)

Ex 8 — Cell G: real aerospace word problem

Forecast: fire alarm ko kaun se numeric IDs milenge?

Step 1 — Urgency ko ID magnitude mein translate karo. Yeh step kyun? Lower ID = higher priority (zyada leading dominant zeros). Isliye sabse urgent message ko sabse chhota number milta hai.

Engine-fire alarm → ID 1 (0b000 0000 0001)
Landing-gear status → ID 256 (0b001 0000 0000)
Cabin-lighting → ID 1024 (0b100 0000 0000)

Step 2 — Simultaneous transmission simulate karo. Yeh step kyun? Bit 10 par: fire 0 drive karta hai, gear 0 drive karta hai, cabin 1 drive karta hai → cabin bit 10 par haarta hai. Bit 8 par: fire 0 drive karta hai, gear 1 drive karta hai → gear haarta hai. Fire alarm har bit survive karta hai.

Answer: fire = 1, gear = 256, cabin = 1024 assign karo → fire alarm hamesha jeetat hai, kuch hi bits mein.

Verify: $1 < 256 < 1024$ toh priority bilkul urgency se match karti hai. ✓ Cabin mein bit 10 set hai ( $1024 = 2^{10}$ ) → pehle out. ✓ Gear mein bit 8 set hai ( $256 = 2^{8}$ ) → agle out. ✓

Ex 9 — Cell H: exam twist — data length aur RTR priority decide NAHI karte

Forecast: kya bada message (zyada bytes) jeetat hai?

Step 1 — ID fields compare karo. Yeh step kyun? Arbitration sirf ID bits use karti hai; DLC aur data frame mein bahut baad aate hain, winner decide hone ke kaafi baad. Isliye "8 bytes vs 0 bytes" jeetne ke liye irrelevant hai.

Step 2 — IDs tie karte hain, toh agla arbitration bit dekho: RTR. Yeh step kyun? 11 ID bits ke baad, RTR bit abhi bhi arbitration window mein hai. D1 (data) RTR = 0 (dominant) drive karta hai; D2 (remote) RTR = 1 (recessive) drive karta hai.

Step 3 — RTR par wired-AND. Bus = 0 AND 1 = 0. D2 ne 1 bheja, 0 read kiya → D2 haarta hai. Data frame jeet jaata hai same ID wale remote frame se.

Answer: D1 (data frame) jeetat hai; priority ID phir RTR se decide hoti hai, data length se kabhi nahi.

Verify: RTR dominant (0) < RTR recessive (1), toh data frame same-ID remote frame ko beat karta hai. ✓ DLC = 8 vs 0 comparison mein kabhi aaya hi nahi → "bada message jeetat hai" intuition galat hai (parent Mistake 4). ✓