Timers — PWM generation, input capture, output compare: Question bank

5.5.3 · D5 · Coding › Embedded Systems & Real-Time Software › Timers — PWM generation, input capture, output compare

Shuru karne se pehle, teen plain-word reminders taaki neeche koi symbol unearned na lage:

CNT = counting register — yeh $0, 1, 2, \dots$ ek step per timer tick chadhhta hai, jaise ghadi ki sui ghoomti hai.
ARR = woh "top" jahan count wrap karta hai. Counter ek lap mein $A R R + 1$ distinct values dikhata hai kyunki yeh $0$ bhi dikhata hai.
CCR = ek threshold/snapshot register. Compare mode mein tum isse likhte ho (yeh decide karta hai ki pin kab flip hogi); capture mode mein hardware isse likhta hai (yeh record karta hai ki jab edge aayi thi tab CNT kahan tha).
PSC = prescaler — source clock ko $(P S C + 1)$ se divide karke ticks slow karta hai.

True or false — justify karo

Timer compare mode pin ko counter ki value ka cause banata hai.

False. Compare/PWM mein counter cause hota hai (Time → Pin): jab CNT, CCR tak pahunchta hai tab hardware pin par action karta hai. Pin ka counter ko drive karna capture hai (Pin → Time), yeh ulta arrow hai.

PSC = 72 set karna ek 72 MHz clock ko exactly 1 MHz tak divide karta hai.

False. Divider

(P S C + 1)

hai, isliye PSC=72 se 73 se divide hoga. 1 MHz ke liye divide-by-72 chahiye toh PSC=71 chahiye. +1 isliye hai taaki PSC=0 se 1 se divide ho, kabhi 0 se nahi.

Ek PWM signal ki frequency tab change hoti hai jab tum duty cycle change karte ho.

False. Frequency ARR se fix hoti hai (poore lap ki length). Duty CCR/(ARR+1) hai — CCR move karne se sirf yeh shift hota hai ki kahan HIGH, LOW mein jaata hai same-length lap ke andar, isliye period aur frequency wahi rehte hain.

CCR = ARR likhne se exactly 100% duty cycle milta hai.

False. True 100% ke liye saare

A R R + 1

ticks mein HIGH chahiye, isliye CCR = ARR+1 chahiye (ya chip ka special force-high). CCR = ARR par pin abhi bhi sirf aakhri ek tick ke liye LOW hoti hai.

Toggle output-compare mode mein, ek match se ek poora output period milta hai.

False. Toggle pin ko flip karta hai, isliye ek period complete karne ke liye do matches chahiye (HIGH→LOW phir LOW→HIGH). Isliye output frequency = match-rate ÷ 2.

Software while-loop mein delay() se PWM karna timer hardware jitna accurate hai.

False. Software timing mein jitter aata hai jab bhi koi interrupt ya doosra task CPU cycles chura leta hai, aur CPU sirf wait karte hue kuch nahi karta aur jalta hai. Timer peripheral pin ko hardware mein exact tick par flip karta hai, CPU kuch bhi kar raha ho, usse independent.

Agar do input captures mein c2 < c1 aaye, toh measurement corrupt hai aur discard karna chahiye.

False. Chhoti doosri value ka matlab usually sirf yeh hai ki counter edges ke beech wrap hua. Actual elapsed count

(c_{2} - c_{1}) mod (A R R + 1)

hai, jo sahi positive value recover kar leta hai — koi data lost nahi hota.

Servo ke liye hume ek duty-cycle percentage compute karni chahiye aur usse CCR set karna chahiye.

False (spirit mein). Ek servo pulse width microseconds mein padhta hai, period ka percentage nahi. Yeh zyada saaf hai ki 1 µs ticks lo aur CCR seedha desired width par set karo (jaise 1.5 ms ke liye 1500), taaki period change hone par tera angle silently rescale na ho.

Counter har cycle mein exactly ARR ticks karta hai.

False. Yeh

A R R + 1

ticks karta hai, kyunki count 0 bhi ek real tick hai. +1 chhod dene se tera period thoda chhota aur PWM frequency thodi zyada ho jaati hai — scope par measurable.

Input capture mein wahi latency problem hai jo polling loop mein pin read karne mein hoti hai.

False. Capture ka yahi toh point hai: hardware CNT ko CCR mein us waqt snapshot karta hai jab edge aati hai, koi bhi software run karne se pehle. Software latency baad mein sirf yeh delay karti hai ki tum snapshot kab padhte ho, recorded time ko nahi.

Error dhundo

"PWM period = ARR / f_clk, isliye ARR=999 aur 72 MHz ke saath period lagbhag 13.9 µs hai."

Do errors hain: yeh prescaler aur +1 ko ignore karta hai. Sahi hai

T = (P S C + 1) (A R R + 1) / f_{c l k}

. Dono +1s aur actual PSC zaroori hain.

"Prescaler 71 set karna matlab har tick 71 clock cycles lambi hai."

Off by one. PSC=71 se

71 + 1 = 72

se divide hota hai, isliye har tick 72 source cycles ki hai, jo

f_{t im} = f_{c l k} /72

deta hai.

"Duty = CCR/ARR × 100%, aur CCR=ARR par tum 100% par ho."

Denominator

A R R + 1

hona chahiye,

A R R

nahi.

C C R / (A R R + 1)

ke saath, 100% tak pahunchne ke liye

C C R = A R R + 1

chahiye;

C C R = A R R

par tum full se thoda kam ho.

"Toggle mode mein 500 kHz square wave banane ke liye mujhe 500 kHz par matches chahiye."

Tumhe 1 MHz par matches chahiye — output se do guna — kyunki do toggles se ek poora period banta hai. Match rate

2 f_{o u t}

honi chahiye.

"c1=65000, c2=500 ek 16-bit timer par, isliye elapsed = 500 − 65000 = −64500 ticks."

Negative result wrap ka clear sign hai. Modulo lagao:

(500 - 65000) mod 65536 = 1036

ticks. Negative elapsed time par kabhi trust mat karo.

"Kyunki capture CNT ko CCR mein likhta hai, main CCR se live counter bhi kisi bhi waqt padh sakta hoon."

CCR mein aakhri edge ka frozen value hota hai, live count nahi. Live value CNT mein hai; CCR sirf agle capture event par update hota hai.

"Maine compare pin ko plain GPIO output set kiya, isliye PWM uspar dikhna chahiye."

Pin ko uski Alternate Function par switch karna padega taaki timer — GPIO output register nahi — use drive kare. Dekho GPIO and Alternate Functions. Plain GPIO mode mein timer ka signal pin tak kabhi nahi pahunchta.

Why questions

Prescaler PSC+1 se kyun divide karta hai instead of PSC se?

Taaki register divide-by-1 express kar sake. Agar yeh PSC se divide karta, toh PSC=0 ka matlab divide-by-0 hota (undefined), aur tum timer ko kabhi full clock speed par run nahi kar sakte. +1 poori range ko ek se upar shift kar deta hai.

Compare ke liye data flow "Time → Pin" aur capture ke liye "Pin → Time" kyun hai?

Compare counter ko trigger ke taur par use karta hai — jab yeh CCR hit karta hai tab hardware pin move karta hai, isliye timer duniya ko command karta hai. Capture external edge ko trigger ke taur par use karta hai — pin event hardware ko counter record karne ke liye kehta hai, isliye duniya timer ko command karti hai. Same compare/capture unit, opposite causal arrow.

Mod capture measurement mein counter overflow ko correctly kyun handle karta hai?

Counter size

A R R + 1

ki ek ring par rehta hai (yeh wapas 0 par wrap karta hai). Ring par do positions subtract karke mod

(A R R + 1)

lene se true forward distance milta hai, chahe ring ka zero beech mein ek baar cross hua ho. Multiple overflows count karne ke liye Interrupts and NVIC dekho.

Hum sirf bada ARR use karke prescaling bilkul skip kyun nahi kar sakte?

ARR ek fixed-width register hai (aksar 16-bit, max 65535). High clock speeds par ek 16-bit ARR period ko overflow hone se pehle sirf itna hi stretch kar sakta hai. Prescaler pehle har tick ko slow karta hai, same ARR ko zyada lambi real time span karne deta hai. Dono knobs milke poori range dete hain — dekho Clock Tree and Prescalers.

25% duty par ek LED flicker ki jagah dim kyun dikhti hai, agar woh sach mein fully on aur off ho rahi hai?

Jab PWM frequency aankhon ki flicker-fusion rate (~kuch sau Hz) se kaafi zyada hoti hai, tab aankh light ko time-average karti hai aur sirf on-time ka fraction perceive karti hai. Isliye 25% on-time 25% brightness jaisi lagti hai, flicker nahi.

Input capture se frequency measure karna ek fixed second mein edges count karne se behtar kyun hai?

Capture ek period directly tick-level precision ke saath measure karta hai, isliye yeh ek single cycle ke andar respond karta hai aur low frequencies par accurate rehta hai jahan edge-counting ko kaafi events ke liye poora second wait karna padta. Edge-counting sirf bahut high, steady frequencies ke liye behtar hai.

Toggle mode automatically perfectly 50%-duty square wave kyun deta hai?

Kyunki har match state ko flip karta hai aur matches even spacing par hote hain, HIGH aur LOW mein se har ek exactly ek match-interval rehta hai. Equal halves ka matlab automatically 50% duty hai — period ke andar koi CCR comparison nahi chahiye.

Edge cases

"HIGH while CNT < CCR" PWM mein CCR = 0 par pin kya karti hai?

CNT < 0 kabhi true nahi hota, isliye pin poore lap mein LOW rehti hai — yeh 0% duty hai, fully-off case.

ARR = 0 set karne par output frequency kya hogi?

Counter mein sirf ek value (0) hai aur yeh har single tick par wrap karta hai, isliye period collapse hokar ek tick ka ho jaata hai. Frequency

f_{t im}

hi ban jaati hai — fastest, degenerate case.

Do capture edges c1 == c2 ke saath aati hain. Iska kya matlab hai?

Ya toh do edges ek hi tick mein aayi (period ek tick se chhota — tumhe barik ticks chahiye) ya counter exact puri laps ka ek multiple wrap hua. Mod

0

deta hai jo ambiguous hai; inhe alag karne ke liye tumhe overflow interrupts bhi track karne padenge.

Measured signal ka period ek poore counter lap se lamba hai. Kya mod formula kaafi hai?

Nahi. Ek single mod sirf ek overflow unwrap karta hai. Multi-lap periods ke liye tumhe overflow interrupts

N

count karne padenge aur elapsed

= N (A R R + 1) + (c_{2} - c_{1})

use karna padega; bare mod spuriously chhota time report karega.

CCR ko ARR+1 se bada set kiya gaya. Kya duty milegi?

CNT kabhi itne bade CCR tak nahi pahunchta, isliye pin poore lap mein HIGH rehti hai — 100% (fully-on) case, counter ke maximum se clamp hua.

Exact wrap moment par, aakhri tick (count = ARR) count hota hai ya skip hota hai?

Yeh count hota hai. Lap

0, 1, \dots, A R R

hai — yeh

A R R + 1

ticks hain — aur sirf ARR dikhane ke baad counter reload hokar 0 par jaata hai. Isse skip karna exactly wahi "period uses ARR not ARR+1" wali galti hai.

Ek motor PWM valid duty par set hai lekin shaft ~15% tak nahi chalti. Timer mein bug hai?

Nahi — yeh motor/driver ka static friction aur dead-zone hai, timer nahi. PWM faithfully commanded duty produce kar raha hai; sirf low duties enough torque deliver nahi karti. Dekho Motor Control and H-Bridges.

Recall Ek-line self-audit

Upar har jawab chhupao aur reason phir se derive karo, sirf verdict nahi. Agar tum har cheez ek picture se explain kar sako (counter ek sweeping clock hand ki tarah, CCR dial par ek mark ki tarah), toh topic tumhara hai.

Connections

GPIO and Alternate Functions — compare/PWM ke reach karne ke liye pin AF mode mein honi chahiye.
Interrupts and NVIC — overflow ISRs capture ko multi-lap periods measure karne dete hain.
Clock Tree and Prescalers — $f_{c l k}$ ka source aur reason ki ARR akela kaafi nahi hai.
Motor Control and H-Bridges — "valid duty, no motion" edge case kahan se aata hai.
Servo and ESC Control — kyun pulse-width, duty-% nahi, sahi mental model hai.
Encoder Mode — ek capture-cousin jahan timer quadrature edges count karta hai.