4.2.37 · D3Operating Systems

Worked examples — I - O management — polling, interrupt-driven, DMA

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The scenario matrix

Every I/O costing question is one (or a mix) of these case classes. Think of it like the quadrants of a coordinate plane: we must cover them ALL, including the degenerate edges.

Cell Case class Distinguishing input Which method should win?
A Slow device, single unit huge, Interrupt
B Fast device, almost-always-ready Polling
C High-rate stream, per-byte interrupt huge, one IRQ/byte Polling beats interrupt (!)
D Large block transfer huge, block-capable DMA
E Crossover / break-even solve for the tie point depends — find threshold
F Degenerate: nothing to transfer all cost setup only
G Limiting: device instant Polling (no wait to overlap)
H Limiting: device never ready Polling waste
I Cycle-stealing correction DMA + bus contention DMA, but CPU not 100% free
J Real-world word problem pick the method reasoning, not just arithmetic
K Exam twist mixed/misleading numbers catch the trap

We now cover A–K with examples. Each example is tagged with the cell(s) it hits.


Worked examples











Recap of the whole matrix

Recall Which method wins in each limit?

(instant device) → wins? ::: Polling — nothing to overlap, interrupt overhead is wasted. (never ready) → polling does what? ::: Spins forever, waste ; interrupts leave CPU free. High byte-rate, one IRQ/byte → polling vs interrupt? ::: Polling can beat interrupt because per byte dominates. Large block transfer → best method? ::: DMA — interrupt count drops from to . degenerate transfer → cheapest method? ::: Polling ( unit); DMA still pays its setup. Break-even between poll and interrupt (single byte)? ::: . Does DMA make the CPU 100% free? ::: No — cycle stealing steals bus cycles, but the loss is tiny vs interrupts.

Related: Context switching (paid on every interrupt), CPU utilization and throughput (what all this optimises), Disk Scheduling (orders the DMA transfers), Memory-mapped I/O vs Port-mapped I/O (how registers are addressed).