Exercises — I - O management — polling, interrupt-driven, DMA

WHAT: It reads the status register. WHY: Status = "device condition" (busy / ready / error). The data register holds bytes; the command register holds orders like "START READ". Only the status register answers "ready?". Does it change anything? No — reading status is a pure query; it does not command the device. (Contrast: writing the command register does cause action.)

• (a) → DMA (block-at-a-time, one interrupt at completion).
• (b) → Polling (busy-wait on the status register).
• (c) → Interrupt-driven (device raises an interrupt line). WHY these and not swapped: the distinguishing question is who watches the status and who moves the bytes. Polling: CPU watches + moves. Interrupt: device signals, CPU moves. DMA: controller watches + moves.

Polling < Interrupt-driven < DMA. WHY: Polling makes the CPU both wait and copy → most CPU work. Interrupts remove the waiting but keep the per-byte copy. DMA removes both the waiting and the copying → least CPU work. Each step "removes more work from the CPU."

WHAT: Wasted polls $\approx \frac{T_{dev}}{t_{poll}}$. WHY this formula: the CPU runs the poll loop back-to-back; in time $T_{dev}$ it fits $T_{dev}/t_{poll}$ iterations, and every one before the last found "not ready" → wasted. Plug in (convert to same units): $T_{dev}=8\text{ms}=8\times 10^6\text{ns}$, $t_{poll}=100\text{ns}$. $\frac{8\times 10^6}{100}=80,000\text{ wasted polls.}$ That's 80,000 iterations of pure waste for one ready event.

WHAT: overhead $=N\cdot t_{int}$. WHY: interrupt-driven I/O pays $t_{int}$ once per data unit, and there are $N$ units. $512\times 40=20,480\text{ units.}$ Notice this grows linearly with $N$ — that's the weakness DMA fixes.

WHAT: DMA raises exactly 1 interrupt (at completion, when count = 0). WHY: the DMA controller handles each byte autonomously; the CPU is told only "block done." Overhead $=1\times t_{int}=1\times 40=40$ units (plus a tiny fixed setup). Compare to L2·Q2's 20,480 units: DMA cut interrupt overhead by a factor of $512$.

WHAT: crossover is where the CPU time saved by not waiting exceeds the interrupt overhead: $T_{dev}>t_{int}$. WHY: if the device is ready almost instantly ($T_{dev}$ tiny), the wait is cheaper than an interrupt's fixed cost → poll. Once $T_{dev}$ exceeds $t_{int}$, the freed CPU time outweighs the overhead → interrupt. Crossover: $T_{dev}=t_{int}=2\mu s$. So for $T_{dev}>2\mu s$ → interrupt-driven wins; for $T_{dev}<2\mu s$ (nearly-ready device) → polling wins. Look at the crossing of the blue (polling) and orange (interrupt) lines in the figure.

WHAT: interrupts per second $=R=10^6$. Time in ISRs per second $=R\cdot t_{int}$. $10^6\times 2\times 10^{-6}\text{s}=2.0\text{ seconds of work per }1\text{ second.}$ WHY this is the point: the CPU would need 200% of its time just to service interrupts — physically impossible. The ISR overhead dominates. Conclusion: at high data rates, per-byte interrupts collapse. This is exactly why DMA exists — move the whole block, interrupt once.

The claim is wrong. DMA and CPU share the memory bus. Each time the DMA controller grabs the bus to move a word, the CPU cannot use memory that cycle and may stall — this is cycle stealing. What IS true: DMA removes the CPU from the byte-copying loop, so its load drops from $O(N)$ to $O(1)$. It is a huge saving — but not contention-free, because both masters compete for the one bus (resolved by bus arbitration). Steel version of the truth: "CPU is free from copying, but not free from occasional bus stalls."

Polling: $N$ moves $+$ wasted polls $=4096+10,000=14,096$ units. (CPU stuck the whole time.) Interrupt-driven: $N$ ISRs $=4096\times 50=204,800$ units of overhead. (Per-byte interrupts hurt at large $N$.) DMA: $1$ setup $+1$ ISR $\approx 50+\epsilon \approx \sim 100$ units, CPU free meanwhile. Rank (best = least CPU work): DMA $⋘$ Polling $<$ Interrupt-driven. WHY the surprise? For large blocks, per-byte interrupts are actually the worst here because $t_{int}$ (50) $\gg$ per-byte poll savings — DMA's block-at-a-time model is the decisive win. This is the parent's "forecast then verify" confirmed. ✅

(a) Keyboard → Interrupt-driven. Rare events (huge $T_{dev}$) ⇒ polling wastes millions of cycles; only 1 byte ⇒ DMA setup isn't worth it. Interrupt = "wake me on the rare ding." (b) NIC → DMA. Huge blocks + high rate ⇒ per-byte interrupts collapse (L3·Q2); block transfer with one completion interrupt is the only sane choice. (c) Always-ready sensor → Polling. $T_{dev}$ is a few ns $<t_{int}$ ⇒ interrupt overhead would exceed the poll cost. Just read it directly. The unifying rule: match technique to the device's rate (how often) and block size (how much). No single method wins everywhere.

(a) Poll vs interrupt. Polling ties up the CPU for the whole wait $\approx T_{dev}$; interrupts cost a fixed $t_{int}$ and free the CPU. Poll only when the expected wait is shorter than the interrupt overhead: $\text{poll if }{T}_{dev}<t_{int}=5\mu s,\text{else interrupt.}$ (At $T_{dev}=5\mu s$ they tie; below it, spinning ~$5\mu s/250\text{ns}=20$ polls is cheaper than one interrupt.)

(b) Switch to DMA when the transfer is a block ($N$ large) and per-byte interrupt cost $N\cdot t_{int}$ would exceed the CPU's time budget — i.e. whenever $N$ is more than a handful of bytes on a fast device. DMA makes cost $O(1)$ instead of $O(N)$.

(c) Pseudocode:

handle_io(request):
    if request.is_block and request.N > SMALL_THRESHOLD:
        setup_DMA(src, dst, N)     # one completion interrupt
    elif expected_Tdev < t_int:     # 5 microseconds
        poll_status_until_ready()   # busy-wait, cheaper here
    else:
        issue_command(); return     # interrupt-driven; ISR finishes it

Defence: each branch is chosen where its cost model is provably lowest — polling for near-instant devices, interrupts for slow single-unit events, DMA for large blocks. This is the parent's "P < I < D offloading" turned into an actual, defensible policy. See CPU utilization and throughput and Context switching (each interrupt costs a context save/restore) for why minimising interrupts matters.

WHAT: solve $\underset{\text{interrupt}}{\underbrace{50N}}>\underset{\text{DMA total}}{\underbrace{S+50}}$. WHY: find the crossover where DMA's constant cost undercuts interrupts' linear cost. $50N>60+50=110\Rightarrow N>\frac{110}{50}=\mathrm{2.2.}$ So for $N\ge 3$ bytes, DMA already wins on CPU work. Interpretation: even for tiny blocks the break-even is small — DMA's $O(1)$ behaviour dominates almost immediately once the transfer is more than a couple of bytes.

Did you get every numeric answer? ::: L2: 80000; 20480; 40. L3: crossover 2 μs; 2.0 s (200%). L4: 14096 / 204800 / ~100. L5: poll if under 5 μs; DMA wins for N ≥ 3; break-even N = 2.2. Did you justify each choice by rate AND block size? ::: If not, re-read L4·Q2. Can you write the driver policy from memory? ::: If not, re-read L5·Q1 pseudocode.