4.1.14 · D3Computer Architecture (Deep)

Worked examples — Virtual memory — concept, page table, virtual-to-physical translation

3,465 words16 min readBack to topic

This page is the drill hall for the parent topic. The parent taught the machine: split the address, look up the page table, concatenate. Here we run that machine on every kind of input it can meet — clean hits, page faults, weird page sizes, the very first byte of a page, the very last byte, a permission error, and an exam-style twist.

Before we start, one promise: we only use ideas already built in the parent. Let us re-anchor the symbols we lean on, in plain words, so nothing sneaks in undefined.

The picture below fixes the geometry of a virtual address once — how a VA splits into VPN + offset, how the VPN becomes a PFN through the table, and how the offset slides straight through to form the PA. Every example points back to it.

Figure — Virtual memory — concept, page table, virtual-to-physical translation

Read it top to bottom: the blue VPN half (bits 31…12) is looked up in the page table and replaced by the green PFN; the orange offset half (bits 11…0) is copied down untouched. That is the whole machine in one figure.


The scenario matrix

Every problem this topic can throw is one (or a mix) of the cells below. The worked examples that follow each announce which cell they cover, and together they fill the whole grid.

# Cell (case class) What makes it special Covered by
C1 Clean hit, generic byte valid=1, offset is somewhere in the middle Ex 1
C2 Offset = 0 (page boundary, first byte) tests that the base address is exactly PFN·2^p Ex 2
C3 Offset = max (last byte of a page) tests the off-by-one edge; next byte crosses into a new page Ex 3
C4 Page fault (valid = 0) data on disk; no PA yet — trap first Ex 4
C5 Protection fault (valid=1 but write to read-only) mapping exists, permission denies it Ex 5
C6 Non-power-of-two-friendly sizing / different page size 1 KiB, 2 KiB, huge pages — recompute the split Ex 6
C7 Degenerate: VA = 0 the very first byte of the whole space Ex 7
C8 Real-world word problem array walk, count how many pages / faults Ex 8
C9 Exam twist: given PA, work backwards to VA reverse the recipe Ex 9
C10 Limiting behaviour: array crossing a page boundary one logical access → two pages Ex 10

Example 1 — the clean hit (cell C1)


Example 2 — offset = 0, page boundary (cell C2)


Example 3 — offset = max, last byte (cell C3)


Example 4 — page fault (cell C4)


Example 5 — protection fault (cell C5)


Example 6 — a different page size (cell C6)


Example 7 — degenerate input, VA = 0 (cell C7)


Example 8 — real-world word problem (cell C8)


Example 9 — exam twist: reverse the recipe (cell C9)


Example 10 — limiting behaviour: a load that straddles two pages (cell C10)

The straddle picture below shows the split of a single word across two frames.

Figure — Virtual memory — concept, page table, virtual-to-physical translation

Active recall

Recall Cover the answers and test yourself

Ex 1 PA for VA 0x7BE4, PFN 0x2C, 4 KiB ::: 0x2CBE4 Ex 6 PA for VA 0x14D6, PFN 0x0C, 1 KiB pages ::: 0x30D6 (= 12502) Ex 8 number of page faults walking 10000 bytes over 4 KiB pages ::: 3 Ex 10: do the two halves of the word land on adjacent physical frames? ::: No — 0x30FFE then 0x71000; adjacency in VA does not imply adjacency in PA Difference between a page fault and a protection fault ::: page fault = valid=0, fetch from disk and retry; protection fault = valid=1 but the operation (e.g. write) is forbidden


Where to go next: the cost of these lookups (they live in RAM!) is tamed by the TLB — Translation Lookaside Buffer; the 4 MiB-per-process table blow-up is fixed by Multi-level Page Tables; and reloading the map on a context switch is Context Switching and CR3 / Page-Table Base Register. Compare the whole scheme with Paging vs Segmentation and see where it sits in the Memory Hierarchy.