Registers — N flip-flops storing N bits — Hinglish notes

1.1.8 · Coding › How Computers Work

Register KIYA hai?

KYA store karta hai: ek $N$ -bit pattern, jaise ki 4-bit register mein 1011.
KYA cheez ise raw flip-flops se alag banati hai: flip-flops synchronised hain (same clock) isliye bits thodi alag timings par nahi badalti — word consistent rehta hai.

KAISE: ek flip-flop se banate hain

Step 1 — Atom: ek D flip-flop

Defining behaviour (iska characteristic equation):

$Q_{next} = D (captured at the clock edge)$

Yeh equation kyun? "Agla stored value = woh data jo maine present kiya." Edges ke beech $Q$ freeze rehta hai, isliye yeh sach mein memory hai, sirf ek wire nahi.

Step 2 — N baar replicate karo

Flip-flops $F F_{0}, F F_{1}, \dots, F F_{N - 1}$ lagao. Wire karo:

data inputs $D_{0} \dots D_{N - 1}$ (woh word jo aap store karna chahte ho),
ek shared clock har flip-flop ko,
outputs $Q_{0} \dots Q_{N - 1}$ (stored word).

$Q_{i}^{next} = D_{i} for all i = 0, 1, \dots, N - 1, at the same clock edge$

Clock share kyun karte hain? Taaki word atomically update ho. Agar har bit ka apna clock hota, toh aap half-old, half-new garbage value read kar sakte the (ek race). Ek clock = ek consistent snapshot.

Figure — Registers — N flip-flops storing N bits

Step 3 — Ek Load (enable) line add karo

Ek bare register har clock edge par khud ko overwrite kar leta. Usually aap chahte ho ki woh hold kare jab tak load karne ko na kaha jaye.

$D_{i} = LOAD \cdot IN_{i} + \overline{LOAD} \cdot Q_{i}$

Toh ek loadable register ka actual update rule yeh hai:

$Q_{i}^{next} = LOAD \cdot IN_{i} + \overline{LOAD} \cdot Q_{i}$

Yeh kyun kaam karta hai: yeh bas ek 2-to-1 multiplexer hai jo "naya data" ya "purana self" select karta hai. Jab LOAD low ho, $Q_{i}^{next} = Q_{i}$ → bit unchanged rehta hai → memory preserved.

Worked examples

Common mistakes

Recall Feynman: 12-saal ke bacche ko samjhao

Socho ek row of light switches, har ek ya toh ON ya OFF — yeh ek bit hai. Ek flip-flop ek aisa switch hai jo wahi reh jaata hai jahan aapne use flick kiya. 8 switches ko ek row mein lagao aur agree karo "hum sab ek hi drumbeat (clock) par palatte hain" — ab aap ek beat mein ek 8-bit pattern set kar sakte ho aur woh freeze reh sakta hai jab tak dobara "load" nahi kaho. Switches ki woh row ek register hai: computer ka chhota, super-fast scratch pad jo woh apne brain ke bilkul paas rakhta hai.

Flashcards

N flip-flops ka ek group jo ek clock share karta hai, ek N-bit word store karta hai jo clock edge par atomically update hota hai.

Ek flip-flop kitne bits store karta hai?

Exactly ek bit (0 ya 1).

Ek N-bit register kitni distinct values hold kar sakta hai?

2^{N}

patterns (range 0 to

2^{N} - 1

unsigned).

Saare flip-flops mein ek single clock kyun share karte hain?

Taaki saare bits simultaneously latch hon aur word atomically update ho, half-updated garbage values se bachne ke liye.

D flip-flop ki characteristic equation kya hai?

Q_{next} = D

, active clock edge par capture hoti hai.

LOAD line kya karta hai, aur update rule kya hai?

Yeh naya data ya purani value hold karna select karta hai:

Q_{i}^{n e x t} = LOAD \cdot IN_{i} + \overline{LOAD} \cdot Q_{i}

Ek bare D-register (bina LOAD ke) har clock edge par kya hota hai?

Woh har edge par apna input reload karta hai, isliye agar input badal jaye toh value hold nahi hoti.

CPU mein registers sabse fast storage kyun hain?

Woh saare bits parallel hardware mein store/read karte hain bilkul logic ke paas, bina kisi addressing ya looping overhead ke.

8-bit register mein sabse bada unsigned value kya hoga?

2^{8} - 1 = 255

Kya N bits ka matlab hai N stored numbers?

Nahi — yeh ek waqt mein EK number store karta hai jis ki width N bits hai; N width hai, values ki count nahi.

Connections

Flip-Flops — 1-bit memory — building block.
D Flip-Flop and the Clock Edge — ek single bit kaise latch hota hai.
Multiplexers — selecting between inputs — LOAD line implement karta hai.
Binary Numbers and 2^N — capacity $2^{N}$ kyun hai.
CPU Architecture — Register File — kai registers grouped aur addressed.
Clock and Synchronous Logic — shared timing signal kyun zaroori hai.
Counters and Shift Registers — registers with feedback jo bits move karte hain.