Question bank — Neuromorphic computing

A neuromorphic chip removes the von Neumann bottleneck by making the memory bus faster. ::: False. It removes the bottleneck by co-locating memory and compute so data barely moves at all — there is no separate bus to speed up. See Von Neumann architecture and In-memory computing. If a Leaky Integrate-and-Fire neuron gets a constant input current, its membrane voltage rises without limit until it fires. ::: False. It charges toward the ceiling $RI$ as $V(t)=RI(1-e^{-t/{\tau }_m})$; if that ceiling is below $V_{th}$ it plateaus and never spikes. The "leak" in LIF means the neuron slowly forgets past input when no current arrives. ::: True. With $I=0$ the equation is $\dot{V}=-V/{\tau }_m$, an exponential decay to rest — old excitation fades. This is the same physics as an RC circuit discharging. Spiking neurons carry information in the height of each spike. ::: False. Spikes are all-or-nothing events; information lives in when they occur and how often (timing/rate), not amplitude. STDP requires a global error signal broadcast to every synapse, like backpropagation. ::: False. STDP is local: each synapse uses only its own pre- and post-spike times $\Delta t$. That locality is exactly what makes it cheap in silicon. Contrast with Hebbian learning. Neuromorphic hardware is always faster than a GPU on any workload. ::: False. Its advantage is energy per inference on sparse, temporal, event-driven data. On dense synchronous matrix math a GPU often wins on raw throughput. A larger membrane time constant ${\tau }_m=RC$ makes a neuron respond faster. ::: False. Larger ${\tau }_m$ means slower charging — the exponential $e^{-t/{\tau }_m}$ takes longer to rise, so time-to-spike grows. Address-Event Representation (AER) is a mandatory feature of every neuromorphic system. ::: False. AER is a common event-communication protocol, but the parent note stresses "many but not all" systems use it — it is a design choice, not a definition. A spiking neuron is stateless, computing a fresh output from inputs each cycle like a ReLU. ::: False. It is a dynamical system with memory: the membrane potential $V(t)$ integrates and leaks over time, so the past shapes the present. See Spiking Neural Networks (SNN).

"Since more input current means more charge, doubling $I$ guarantees the neuron fires." ::: The error: it ignores the leak. The steady ceiling is $RI$; if $RI\le V_{th}$ it never fires no matter how long you wait. You must compare $RI$ to $V_{th}$, not just increase $I$ blindly. "The STDP branch is chosen by whether $\Delta w$ is positive or negative." ::: Backwards. The sign of $\Delta t=t_{post}-t_{pre}$ chooses the branch; the branch then produces the sign of the weight change $\Delta w$. You cannot use the output to pick the rule that made it. "In LIF the minus sign in ${\tau }_m\dot{V}=-V+RI$ is just a convention and could be plus." ::: No — the minus encodes the leak/decay. Flip it to plus and $V$ would blow up exponentially with no input, which is physically the opposite of a leaky membrane. "Neuromorphic chips save power because their transistors are smaller." ::: The real reason is event-driven sparsity: idle neurons stay silent and consume near-zero power, and data does not shuttle across a bus. Feature size is a separate, orthogonal factor. "A memristor stores a synaptic weight but still needs a separate processor to do the multiply." ::: The point of a memristor crossbar is that the device itself performs the weighted multiply-and-sum in place — that is In-memory computing, not a separate multiply step. "Firing rate equals input current, so it grows linearly with $I$." ::: No. From $T={\tau }_m\ln \frac{RI}{RI-V_{th}}$, the rate $1/T$ is a nonlinear function of $I$ — near threshold it jumps from zero, then rises sub-linearly, saturating for large $I$.

Why model the neuron membrane as an RC circuit specifically? ::: The lipid membrane separates charge like a capacitor $C$, and ion channels let charge leak back like a resistor $R$. Together that is literally an RC circuit driven by input current. Why does STDP use exponential functions of $\Delta t$ rather than, say, a step function? ::: Causal influence fades smoothly with the timing gap: a spike arriving 100 ms early barely contributed, so its weight change $\Delta w$ should shrink continuously as $|\Delta t|$ grows. Why is co-locating memory and compute such a big energy win? ::: Because in a Von Neumann architecture most energy goes into moving data over the bus, not computing. Keep the weight next to the multiply and that transport cost vanishes. Why does the threshold-and-reset rule matter — isn't the differential equation enough? ::: The ODE alone only produces a smooth analog voltage; it never spikes. The ==nonlinear threshold $V_{th}$ + reset is what turns a leaky integrator into a discrete-event, spiking unit. Why is sparsity, not parallelism alone, the key to the brain's ~20 W efficiency? ::: Parallelism spreads work out, but event-driven silence means most units burn no energy at any instant. You pay only for the spikes that actually fire. Why can STDP be called a "sharpened Hebb's rule"? ::: Hebb says "fire together, wire together"; STDP adds causal timing==: pre-before-post strengthens (it may have helped cause the spike), pre-after-post weakens. See Hebbian learning.

What happens when $RI=V_{th}$ exactly? ::: The log argument $\frac{RI}{RI-V_{th}}$ diverges to $+\infty$, so $T\to \infty$: the neuron asymptotically approaches threshold but takes infinite time — effectively it never fires. What happens when $RI<V_{th}$? ::: The ceiling is below threshold; $V$ plateaus at $RI$ and the formula's log argument goes negative (undefined). The neuron sits silent forever — this silence is the energy saving. What if the input current is negative, $I<0$? ::: The ceiling $RI$ becomes negative, so the membrane is driven below rest (hyperpolarized). It moves away from $V_{th}$, never fires, and only makes the neuron harder to excite until the current is removed. What is $\Delta w$ under STDP when $\Delta t=0$ (pre and post spike simultaneously)? ::: The two exponential branches meet at the discontinuity $t_{post}=t_{pre}$; the rule is undefined/ambiguous at exactly zero. Real chips pick a convention (often no update) since exact coincidence carries no causal direction. If input current $I(t)=0$ but the membrane starts charged at $V_0$, what does $V(t)$ do? ::: It decays as $V(t)=V_0{e}^{-t/{\tau }_m}$ toward rest — pure leak, no firing, the neuron forgetting its charge. A neuron receives one tiny spike far below threshold, then nothing for a long time. Does it eventually fire? ::: No. The single small increment leaks away exponentially before it can accumulate; without sustained or coincident input, $V$ returns to rest and no spike occurs. In the limit ${\tau }_m\to \infty$ (no leak, a pure integrator), how does the neuron behave? ::: With ${\tau }_m$ huge the leak term vanishes and $C\dot{V}\approx I$, so $V$ rises linearly and never forgets — it perfectly accumulates every bit of input. It always eventually fires for any $I>0$, the opposite of the leaky hard-threshold behaviour. In the limit ${\tau }_m\to 0$ (no memory), what kind of unit does LIF become? ::: It stops integrating over time — the voltage tracks the instantaneous input with no leak-memory, collapsing toward a memoryless threshold gate rather than a temporal, dynamical neuron. What happens to firing rate as $I\to \infty$? ::: $T={\tau }_m\ln \frac{RI}{RI-V_{th}}\to {\tau }_m\ln 1=0$, so the rate saturates upward — but a real neuron caps it via a refractory period the idealized formula ignores.