Question bank — Neuromorphic computing

Ek neuromorphic chip von Neumann bottleneck ko memory bus faster banake remove karta hai. ::: Galat. Yeh bottleneck ko memory aur compute ko saath rakhke remove karta hai taaki data bilkul bhi move na ho — koi alag bus hi nahi hai jise speed up karna ho. Von Neumann architecture aur In-memory computing dekho. Agar ek Leaky Integrate-and-Fire neuron ko constant input current milta hai, to uska membrane voltage fire karne tak bina limit ke badhta rehta hai. ::: Galat. Yeh $V(t)=RI(1-e^{-t/{\tau }_m})$ ki tarah ceiling $RI$ ki taraf charge hota hai; agar woh ceiling $V_{th}$ se neeche hai to yeh plateau kar jaata hai aur kabhi spike nahi karta. LIF mein "leak" ka matlab hai neuron jab koi current nahi aata to past input ko dheere dheere bhool jaata hai. ::: Sahi. $I=0$ ke saath equation hai $\dot{V}=-V/{\tau }_m$, rest tak exponential decay — purani excitation fade ho jaati hai. Yahi physics hai RC circuit discharge hone ki. Spiking neurons mein information har spike ki height mein hoti hai. ::: Galat. Spikes all-or-nothing events hain; information kab hote hain aur kitni baar (timing/rate) mein hoti hai, amplitude mein nahi. STDP ko har synapse tak broadcast kia gaya ek global error signal chahiye, backpropagation ki tarah. ::: Galat. STDP local hai: har synapse sirf apne khud ke pre- aur post-spike times $\Delta t$ use karta hai. Yahi locality hai jo ise silicon mein sasta banati hai. Hebbian learning se contrast karo. Neuromorphic hardware kisi bhi workload par GPU se hamesha faster hota hai. ::: Galat. Iska advantage sparse, temporal, event-driven data par energy per inference hai. Dense synchronous matrix math par GPU aksar raw throughput mein jeet jaata hai. Bada membrane time constant ${\tau }_m=RC$ neuron ko faster respond karta hai. ::: Galat. Bada ${\tau }_m$ matlab slower charging — exponential $e^{-t/{\tau }_m}$ rise hone mein zyada time leta hai, to time-to-spike badhta hai. Address-Event Representation (AER) har neuromorphic system ki mandatory feature hai. ::: Galat. AER ek common event-communication protocol hai, lekin parent note stress karta hai ki "bahut saare lekin sab nahi" systems ise use karte hain — yeh ek design choice hai, definition nahi. Ek spiking neuron stateless hota hai, har cycle mein inputs se fresh output compute karta hai jaise ReLU. ::: Galat. Yeh ek dynamical system with memory hai: membrane potential $V(t)$ time ke saath integrate aur leak karta hai, to past present ko shape karta hai. Spiking Neural Networks (SNN) dekho.

"Kyunki zyada input current matlab zyada charge hai, $I$ double karna guarantee karta hai ki neuron fire karega." ::: Error: yeh leak ko ignore karta hai. Steady ceiling hai $RI$; agar $RI\le V_{th}$ ho to yeh kabhi fire nahi karega chahe kitna bhi wait karo. Tumhe $RI$ ko $V_{th}$ se compare karna hoga, blindly sirf $I$ nahi badhana. "STDP branch is chosen by whether $\Delta w$ is positive or negative." ::: Ulta hai. $\Delta t=t_{post}-t_{pre}$ ka sign branch choose karta hai; branch tab weight change $\Delta w$ ka sign produce karta hai. Tum output use nahi kar sakte usse banane wala rule choose karne ke liye. "${\tau }_m\dot{V}=-V+RI$ mein LIF ka minus sign sirf ek convention hai aur plus bhi ho sakta tha." ::: Nahi — minus leak/decay encode karta hai. Ise plus kar do aur $V$ bina input ke exponentially blow up ho jaayega, jo physically leaky membrane ke bilkul opposite hai. "Neuromorphic chips power save karte hain kyunki unke transistors chhote hote hain." ::: Asli reason hai event-driven sparsity: idle neurons silent rehte hain aur near-zero power consume karte hain, aur data bus ke across shuttle nahi karta. Feature size ek alag, orthogonal factor hai. "Ek memristor synaptic weight store karta hai lekin multiply karne ke liye phir bhi alag processor chahiye." ::: Memristor crossbar ka point yahi hai ki device khud weighted multiply-and-sum in place perform karta hai — yahi In-memory computing hai, alag multiply step nahi. "Firing rate input current ke barabar hai, to yeh $I$ ke saath linearly badhti hai." ::: Nahi. $T={\tau }_m\ln \frac{RI}{RI-V_{th}}$ se, rate $1/T$ $I$ ka ek nonlinear function hai — threshold ke paas yeh zero se jump karta hai, phir sub-linearly badhta hai, bade $I$ ke liye saturate hota hai.

Neuron membrane ko specifically RC circuit kyun model karte hain? ::: Lipid membrane charge ko ek capacitor $C$ ki tarah separate karta hai, aur ion channels charge ko ek resistor $R$ ki tarah vapas leak karne dete hain. Saath milke yeh literally ek RC circuit hai jo input current se drive hota hai. STDP $\Delta t$ ke exponential functions use karta hai rather than, say, a step function? ::: Causal influence timing gap ke saath smoothly fade hota hai: 100 ms pehle aaya spike barely contribute kiya hoga, to uska weight change $\Delta w$ continuously sirakna chahiye jab $|\Delta t|$ badhta hai. Memory aur compute ko saath rakhna itna bada energy win kyun hai? ::: Kyunki Von Neumann architecture mein zyaadatar energy data ko bus par move karne mein jaati hai, compute mein nahi. Weight ko multiply ke paas rakho aur woh transport cost khatam ho jaati hai. Threshold-and-reset rule kyun matter karta hai — kya differential equation kaafi nahi hai? ::: ODE akela sirf smooth analog voltage produce karta hai; yeh kabhi spike nahi karta. ==Nonlinear threshold $V_{th}$ + reset hi woh hai jo leaky integrator ko ek discrete-event, spiking unit mein turn karta hai. Sparsity, parallelism akela nahi, brain ki ~20 W efficiency ki key kyun hai? ::: Parallelism kaam phailata hai, lekin event-driven silence matlab hai ki zyaadatar units kisi bhi instant par zero energy burn karte hain. Tum sirf un spikes ke liye pay karte ho jo actually fire hote hain. STDP ko "sharpened Hebb's rule" kyun kaha ja sakta hai? ::: Hebb kehta hai "fire together, wire together"; STDP causal timing== add karta hai: pre-before-post strengthen karta hai (usne spike cause kiya hoga), pre-after-post weaken karta hai. Hebbian learning dekho.

Jab $RI=V_{th}$ exactly ho tab kya hota hai? ::: Log argument $\frac{RI}{RI-V_{th}}$ $+\infty$ tak diverge karta hai, to $T\to \infty$: neuron asymptotically threshold ke paas approach karta hai lekin infinite time leta hai — effectively kabhi fire nahi karta. Jab $RI<V_{th}$ ho tab kya hota hai? ::: Ceiling threshold se neeche hai; $V$ $RI$ par plateau karta hai aur formula ka log argument negative ho jaata hai (undefined). Neuron hamesha ke liye silent baitha rehta hai — yahi silence energy saving hai. Agar input current negative ho, $I<0$? ::: Ceiling $RI$ negative ho jaata hai, to membrane rest ke neeche drive hoti hai (hyperpolarized). Yeh $V_{th}$ se door jaati hai, kabhi fire nahi karti, aur neuron ko excite karna aur mushkil ho jaata hai jab tak current remove na ho. STDP ke under $\Delta w$ kya hoga jab $\Delta t=0$ ho (pre aur post spike simultaneously)? ::: Do exponential branches discontinuity $t_{post}=t_{pre}$ par milte hain; rule exactly zero par undefined/ambiguous hai. Real chips ek convention choose karte hain (aksar no update) kyunki exact coincidence koi causal direction nahi carry karta. Agar input current $I(t)=0$ lekin membrane $V_0$ par charged shuru ho, to $V(t)$ kya karta hai? ::: Yeh rest ki taraf $V(t)=V_0{e}^{-t/{\tau }_m}$ ki tarah decay karta hai — pure leak, no firing, neuron apna charge bhool raha hai. Ek neuron ko threshold se kaafi neeche ek tiny spike milti hai, phir kaafi der tak kuch nahi. Kya yeh eventually fire karega? ::: Nahi. Single small increment exponentially leak ho jaata hai usse accumulate hone se pehle; sustained ya coincident input ke bina, $V$ rest par wapas aa jaata hai aur koi spike nahi hoti. Limit ${\tau }_m\to \infty$ mein (no leak, pure integrator), neuron kaise behave karta hai? ::: Bade ${\tau }_m$ ke saath leak term vanish ho jaati hai aur $C\dot{V}\approx I$, to $V$ linearly badhta hai aur kabhi nahi bhoolata — yeh har input ko perfectly accumulate karta hai. Kisi bhi $I>0$ ke liye yeh hamesha eventually fire karta hai, leaky hard-threshold behaviour ke bilkul opposite. Limit ${\tau }_m\to 0$ mein (no memory), LIF kaisi unit ban jaati hai? ::: Yeh time ke saath integrate karna band kar deti hai — voltage bina kisi leak-memory ke instantaneous input track karta hai, ek memoryless threshold gate ki taraf collapse karta hai na ki ek temporal, dynamical neuron. Firing rate jab $I\to \infty$ ho tab kya hota hai? ::: $T={\tau }_m\ln \frac{RI}{RI-V_{th}}\to {\tau }_m\ln 1=0$, to rate upar saturate hoti hai — lekin ek real neuron ise refractory period ke zariye cap karta hai jo idealized formula ignore karta hai.