Open hardware ecosystem (OpenRISC, OpenTitan): Foundations

This page assumes nothing. Every letter, arrow, and word used in the parent note is built here from the ground up, in an order where each idea leans only on the ones before it.

1. What a "chip" is really made of

Before any letters appear, picture what a chip is. A chip is a slab of silicon covered in billions of tiny switches called transistors. On their own they are meaningless — they only do something useful once they are wired into patterns that add, compare, and remember numbers.

The picture below shows this ladder: switches → gates → circuit.

Figure — Open hardware ecosystem (OpenRISC, OpenTitan)

Why the topic needs this: the whole note is about publishing the wiring diagram of these gates. To understand "open the design", you first need to know the design is this pattern of gates — nothing more mystical than a very large, very small electrical drawing.

2. RTL — the "source code" of hardware

Nobody draws a billion gates by hand. Engineers describe the wiring in a text language, and a program lays out the gates automatically — exactly like a programmer writes code and a compiler produces the machine instructions.

Why the topic needs this: the parent's definition of open hardware is literally "the RTL is published under a permissive license." Without knowing what RTL is, that sentence is empty.

See FPGA & RTL Verification for how RTL gets tested and turned into a real device.

3. ISA vs. microarchitecture vs. toolchain (three things people fuse into one)

The parent note insists these are three separate layers that can each be open or closed. Here is the picture that keeps them apart.

Why the topic needs this: OpenRISC is open at the ISA layer; OpenTitan is open at all three. You cannot compare them without this vocabulary.

Related idea: Kerckhoffs's Principle — a system should stay secure even when its design (the rulebook) is public.

4. RISC and the fixed instruction width

The "R" in RISC-V and OpenRISC stands for RISC: Reduced Instruction Set Computer. One design choice from RISC drives a formula in the parent note, so we build it now.

Now the letters. We want a formula, so we must first name the quantities:

Why the topic needs this: the parent uses $Bytes = 4 N$ and $P C_{next} = P C + 4$ ; both are meaningless until $N$ , $w$ , byte, and $P C$ are defined.

5. The security symbols: $H$ , $σ$ , keys, and fuses

The Root-of-Trust part of the topic introduces a small cluster of notation all at once. We define each, tie it to a picture, and say what it answers.

5a. The hash $H$

5b. The signature $σ$ and keys $p k$

A fingerprint alone proves the data hasn't changed since the fingerprint was taken — but an attacker could replace both the image and its fingerprint. We need proof the fingerprint came from the real vendor. That is what a signature adds.

The figure below shows integrity (hash) versus authenticity (signature) side by side.

5c. Where trust bottoms out: eFuses

Every "verify" needs a trusted copy of $p k$ . Where does that live so an attacker can't swap it? In fuses that can be written once and never rewritten.

Why the topic needs all of 5: the parent's secure-boot formula $m_{i} = H (I_{i})$ and $Verify_{p k} (σ_{i}, m_{i}) = true$ uses $H$ , $m$ , $I$ , $σ$ , $p k$ , subscripts $i$ , and "fuses" — every one is defined above.

6. Subscripts and the chain

The parent writes $I_{i}$ , $m_{i}$ , $σ_{i}$ with a little $i$ . That subscript is just a stage counter: $i = 0$ is the first boot stage, $i = 1$ the next, and so on. "Stage $i$ verifies stage $i + 1$ before running it" is the chain of trust — an unbroken line of vouchers from the fused key up to the operating system.

Prerequisite map

Equipment checklist

Self-test: can you answer each before reading on in the parent note?

What is RTL, and what everyday thing is it analogous to?

The text description of a circuit in Verilog/VHDL; it is the "source code" of hardware.

Name the three independent layers that can each be open.

The ISA (rulebook), the microarchitecture/RTL (one implementation), and the toolchain (compiler/EDA tools).

Why does a fixed 32-bit instruction width give

P C_{next} = P C + 4

Every instruction is 4 bytes, so the next address is always +4 with no decoding needed.

Compute the code size of a 10-instruction OpenRISC program.

4 \times 10 = 40

bytes.

What does a hash

H (I)

give you, and what question does it answer?

A short fingerprint of the image; it answers "is this exactly the code I expected?" (integrity).

Why isn't a hash alone enough for secure boot?

It proves integrity but not authenticity — an attacker could swap both the image and its hash; a signature binds the hash to the vendor's private key.

What does the subscript

i

I_{i}, m_{i}, σ_{i}

mean?

It is the boot-stage number in the chain of trust.

Why are the public key stored in one-time-programmable fuses?

So the trust anchor cannot be rewritten by an attacker.