Dynamic voltage and frequency scaling (DVFS)

6.4.2 · Hardware › Power, Thermal & Reliability

What is DVFS?

WHY yeh valuable hai?

Energy savings: Mobile devices battery pe 2-3× zyada chalte hain
Thermal management: Overheating rokta hai bina emergency levels pe throttle kiye
Performance flexibility: Demanding tasks ke liye boost, light work ke liye coast
Reliability: Lower temperatures → components ki longer lifetime

The Physics: Power Laws

Chalte hain first principles se derive karte hain ki DVFS itna effective kyun hai.

Formula Dynamic Power Derivation

Step 1: Capacitive Load Charging Har baar jab ek CMOS gate switch karta hai, woh ek capacitance C ko charge/discharge karta hai. C ko voltage V tak charge karne ki energy: $E_{switch} = \frac{1}{2} C V^{2}$

WHY yeh formula? Ek capacitor mein stored energy hai $\int_{0}^{V} V \cdot d Q = \int_{0}^{V} V \cdot C d V = \frac{1}{2} C V^{2}$ . Jab gate switch karta hai, yeh energy supply se draw hoti hai, phir charging ke waqt heat ke roop mein dissipate hoti hai.

Step 2: Switching Rate Agar clock frequency $f$ hai, aur average mein fraction $α$ (activity factor) gates har cycle mein switch karte hain: $N_{switches} = α \cdot f$ Step 3: Total Dynamic Power Power = Energy per second: $P_{dynamic} = E_{switch} \times N_{switches} = \frac{1}{2} C V^{2} \cdot α f$

Simplified form: $P_{dynamic} = C_{eff} \cdot V^{2} \cdot f$ jahan $C_{eff} = \frac{1}{2} α C$ saare constants ko combine karta hai.

KEY INSIGHT: Power frequency mein linear hai lekin voltage mein quadratic hai. Yahi asymmetry hai jis ki wajah se DVFS dono ko saath pair karta hai.

Yahi fundamental constraint hai: correct operation maintain karne ke liye voltage aur frequency saath scale honi chahiye.

How DVFS Works: Operating Points

HOW system choose karta hai?

Monitor: CPU utilization, instruction throughput, temperature sensors
Predict: Agle 10-100ms window ke liye workload estimate karo
Decide: Woh P-state select karo jo minimum power mein performance target meet kare
Execute: Voltage regulator aur PLL ko transition ke liye command karo (~10-100μs latency)

Common Mistakes and Misconceptions

Common mistake Mistake 2: "DVFS saari power waste eliminate kar deta hai"

Why this feels right: Agar hum frequency ko workload se perfectly match karein, toh hum kabhi zarurath se zyada fast nahi chalate.

Why it's wrong: Do power components exist karte hain: $P_{total} = dynamic C V^{2} f + static V \cdot I_{leak}$

Static leakage power continuously flow karta hai jab transistors powered hote hain, switching se regardless. Modern deep-submicron processes (7nm, 5nm) mein leakage total power ka 20-40% ho sakta hai!

WHY this matters: Bahut low frequencies pe, static power dominate karta hai aur DVFS efficiency drop ho jaati hai. Kabhi kabhi "race-to-idle" (fast chalao, finish karo, so jao) better hota hai compared to slowly chalate rehne aur power leak karte rehne se.

The fix: Maximum savings ke liye DVFS ko power gating (unused cores/blocks ko completely shut off karna) ke combination mein use karo.

Common mistake Mistake 3: "Lower voltage always means lower power"

Why this feels right: $P \propto V^{2}$ , toh V reduce karo → P reduce karo.

Why it's wrong: Agar tum voltage reduce karo lekin frequency nahi reduce karo kaafi:

Timing violations hote hain (logic clock edge se pehle settle nahi hoti)
Processor ya toh crash ho jaata hai ya wait states insert karne padte hain
Effective throughput drop hoti hai, task zyada lambe time leta hai, possibly zyada total energy use karta hai

Example: V 30% lower karo lekin f sirf 10% reduce karo. Transistor delays 50% badh jaate hain, timing violate hoti hai. CPU stalls insert karta hai, effective rate 0.9f se neeche girta hai, task zyada time leta hai, energy badh jaati hai.

The fix: Manufacturer ke specified voltage-frequency curve ko hamesha respect karo. V-f pairs ko timing closure ensure karne ke liye characterize kiya jaata hai.

DVFS Control Policies

HOW decide karein kab scale karna hai?

Example pseudocode (on-demand):

def dvfs_controller(current_pstate, utilization):
    if utilization > 0.8 and current_pstate > 0:
        # Scale up
        return current_pstate - 1
    elif utilization < 0.3 and current_pstate < MAX_PSTATE:
        # Scale down
        return current_pstate + 1
    else:
        # Hold steady
        return current_pstate

WHY yeh thresholds? Empirically tune kiye gaye hain. Bahut aggressive (80%→90%) power waste karta hai; bahut conservative (80%→50%) opportunities miss kar deta hai.

Practical Considerations

Modern extensions:

Per-core DVFS: Different cores different P-states pe (big.LITTLE architectures)
Turbo boost: Temporarily nominal P0 se exceed karo agar thermal headroom allow kare
Package-level coordination: CPU + GPU + memory ke across power balance karo

Connections

Power consumption models: DVFS dynamic power component ko target karta hai
Clock generation and PLs: Frequency scaling PLL control ke through implement hoti hai
Voltage regulators: DVFS ke liye adjustable Vdd supply karte hain
Thermal management: DVFS ek key thermal control mechanism hai
CPU scheduling: OS scheduler ko P-state transitions samajhni chahiye
Real-time systems: DVFS WCET analysis ko complicate karta hai
Race-to-idle vs race-to-dark: Energy efficiency strategy debates
Power gating: Static power ke liye complementary technique
Processor performance counters: DVFS policies ke liye utilization data provide karte hain

Recall Feynman Technique: Ek 12-saal ke bachche ko explain karo

Okay, socho tumhare paas ek super-fast remote control car hai. Jab tum use top speed pe race karo, motor bahut hot hoti hai aur battery super fast drain hoti hai. Lekin zyada tar time, tum use slowly room mein ghuma rahe ho, right?

Kya hoga agar tumhari car itni smart ho ki woh jaane: "Hey, main abhi slowly cruise kar raha hoon, mujhe full power nahi chahiye!" Toh woh motor speed down kar le AUR battery voltage bhi reduce kar le jo use feed ho raha hai. Car thodi slow jaati hai, lekin WAY kam battery use karti hai (kyunki kam voltage = kam power, squared!) aur bahut cool rehti hai.

Phir, jab tum dobara race karna chaho, sab kuch turant back up ho jaata hai!

Exactly yahi tumhara phone ya laptop DVFS ke saath karta hai. Jab tum sirf ek article padh rahe ho, woh slow aur cool chalta hai, battery bachata hai. Jab tum ek game open karo, woh full power pe speed up ho jaata hai. "Voltage aur frequency" car ki battery voltage aur motor speed ki tarah hain — yeh saath adjust hote hain jo tum kar rahe ho use match karne ke liye. Isse tumhari battery 2-3 times zyada chalti hai!

Flashcards

#flashcards/hardware

What is Dynamic Voltage and Frequency Scaling (DVFS)? :: Ek power management technique jo dynamically processor ki supply voltage (V) aur clock frequency (f) ko runtime pe workload demand ke based pe adjust karti hai taaki performance aur power consumption balance ho sake.

Why must voltage and frequency scale together in DVFS?

Lower voltage transistor switching delay badha deti hai (t_delay ∝ V/(V-Vth)²), isliye frequency reduce karni padti hai taaki logic next clock edge se pehle complete ho sake. Warna, timing violations hoti hain.

What is the formula for dynamic power in CMOS circuits?

P_dynamic = C·V²·f, jahan C effective capacitance hai, V supply voltage hai, aur f clock frequency hai. Power frequency mein linear hai lekin voltage mein quadratic hai.

Why is reducing voltage more effective than reducing frequency alone for power savings?

Power∝ V²·f. Voltage ko factor k se reduce karne par k² power reduction milti hai, jabki frequency ko k se reduce karne par sirf k reduction milti hai. Voltage pe quadratic dependence zyada savings deti hai.

If voltage and frequency are both reduced by 30% (k=0.7), what is the energy savings?

Energy per task = V²·N (N cycles ke liye). Nayi energy = (0.7V)²·N = 0.49·V²·N. Savings = 1 - 0.49 = 51%. Task 43% zyada time leta hai lekin 51% kam energy use karta hai.

What are P-states in DVFS?

Discrete operating points (voltage, frequency pairs) jo validated stable configurations define karte hain. P0 maximum performance hai, higher P-numbers progressively lower power states hain.

What is the activity factor (α) in dynamic power equations?

Ek given clock cycle mein switch hone wale transistors ka fraction. Dynamic power = ½·α·C·V²·f. Typical α workload ke basis pe 0.1 se 0.3 tak hota hai.

What is static (leakage) power and why does it matter for DVFS?

P_static = V·I_leak, woh power jo leakage currents se consume hoti hai jab transistors switch nahi kar rahe hote. Bahut low frequencies pe, static power dominate karta hai aur DVFS efficiency drop hoti hai. Modern processes mein, leakage total power ka 20-40% ho sakta hai.

What is the race-to-idle vs. race-to-dark debate?

Race-to-idle: high frequency pe chalo, jaldi finish karo, phir so jao (power gate). Race-to-dark: continuously low power pe slow chalo. Kaun better hai yeh static vs. dynamic power ratio aur sleep/wake overhead pe depend karta hai.

What is the typical latency for a DVFS transition?

Voltage regulator aur PLL stabilize karne ke liye 10-100 microseconds. Transition ke dauran, CPU stall ho sakta hai, aur transition khud energy consume karta hai, isliye frequent switching savings negate kar sakta hai.

Why can't DVFS be used aggressively in hard real-time systems?

Real-time systems ke deadlines minimum frequency require karti hain. Agar deadline meet karne ke liye f_min available f_max se zyada ho, ya DVFS transition latency timing guarantees tod de, toh DVFS real-time constraints violate kiye bina apply nahi ho sakta.

What is hysteresis in DVFS policies?

P-states change karne se pehle sustained high ya low utilization ka wait karna (e.g., 1-10ms stability window). Jittery oscillation states ke beech prevent karta hai aur ensure karta hai ki transition overhead amortize ho.

What is per-core DVFS?

Modern capability jahan har CPU core independently different P-states pe operate kar sakta hai. Heterogeneous computing enable karta hai (e.g., big.LITTLE: high-power cores high P-state pe, efficient cores low P-state pe).

How does DVFS help with thermal management?

Jab temperature threshold exceed kare, DVFS turant lower P-state pe drop karta hai, power dissipation aur heat generation reduce karta hai. Yeh emergency throttling ki jagah graceful performance degradation provide karta hai.

What is the on-demand DVFS policy? :: Reactive policy jo frequency scale up karti hai agar CPU utilization ek threshold exceed kare (e.g., 80%) aur scale down karti hai agar utilization doosre threshold se neeche aaye (e.g., 30%). Fast response lekin hysteresis ke bina jittery ho sakti hai.