Foundations — Vector - SIMD instructions (SSE, AVX, NEON)

This page is the workshop bench. Before you can read the parent note Vector - SIMD instructions (SSE, AVX, NEON), you need to feel every symbol it throws at you. We build each one from nothing: plain words → a picture → why the topic can't live without it.

1. A "bit" and a "byte" — the atoms of everything

Why start here? Because every "register width" the parent brags about — 128-bit, 256-bit, 512-bit — is just how many switches sit in a row. If you don't picture the row of switches, "256-bit register" is a spell, not a fact.

Look at the red byte in the figure: 8 switches, and the pattern shown reads as the number 20. That single number will later be "the brightness we add to a pixel."

2. A "register" — the CPU's tiny desk

Picture a whiteboard the CPU writes one number on, erases, writes the next. A scalar register holds exactly one number.

The whole trick of SIMD is: make the whiteboard so wide it holds a whole row of numbers, and let one command act on the entire row.

3. A "lane" — one slot in the wide desk

Why the topic needs this word: the parent says "operates on all lanes." That is the entire SIMD promise. One instruction fires the starting pistol; all four runners step forward together.

4. "Float", "double", "8-bit int" — what kind of number sits in a lane

Why it matters: the format decides how many lanes fit. Same 128-bit box, different tenants:

Read across: a narrower number means more lanes means bigger speed-up. That single table explains why image code (8-bit pixels) gets 16× while double-precision science gets only 2×.

5. "Packed" and "contiguous" — how the row gets loaded

Why the topic needs this: SIMD's single grab (movaps) works only if the data is already in a neat row. Scattered data must be gathered first, which is slow. This is the seed of Cache Optimization and Loop Vectorization — arrange your data as a row and the hardware rewards you.

6. Sigma $\sum$ — "add up a whole list"

Why the topic needs it: this exact expression is the dot product in Example 2. When the parent multiplies lane-by-lane and then "horizontally sums," it is literally computing this $\sum$. Meet the symbol before it ambushes you.

7. Ceiling $\lceil \rceil$ — "always round up"

Why the topic needs it: if you have 10 numbers but lanes come in groups of 8, you need 2 instructions — the second one still fires even though it only carries 2 real numbers. You can't do "1.25 instructions." The ceiling captures that leftover-group truth, and it's exactly why the parent warns about loop remainders.

8. Speed-up $S$ — the payoff number

Now every piece of the parent's boxed result $S\approx w$ is a symbol you have already met: $T$ is time, $w$ is lane count from §3, and the ceiling from §7 is why it's approximately $w$ and not exactly $w$.

9. Same-instruction rule — the golden constraint

This constraint places SIMD inside Flynn's Taxonomy as the SIMD class (one instruction stream, many data streams), and makes it the hardware engine behind Data Paralelism.

Prerequisite map

Everything on the left is a plain picture; everything flows right into the parent topic. If any left-hand box is fuzzy, re-read that section before moving on. This map also shows the on-ramps to Loop Vectorization, Auto-vectorization, and Instruction-Level Parallelism — all of which reuse these same atoms.

Equipment checklist

Cover the right side and answer out loud; reveal to check.

Next stop: Vector - SIMD instructions (SSE, AVX, NEON) — you now own every symbol it uses.