Vector - SIMD instructions (SSE, AVX, NEON): Foundations

6.1.11 · D1 · Hardware › Parallelism & Multicore › Vector - SIMD instructions (SSE, AVX, NEON)

Yeh page workshop bench hai. Parent note Vector - SIMD instructions (SSE, AVX, NEON) padhne se pehle, tumhe har us symbol ko feel karna hai jo woh tumhare saamne fenk ta hai. Hum har ek cheez zero se banate hain: seedhe words → ek picture → kyun is topic ko yeh cheez zaroori hai.

1. "Bit" aur "byte" — har cheez ke atoms

Yahan se shuru kyun? Kyunki parent note jo bhi "register width" ki baat karta hai — 128-bit, 256-bit, 512-bit — woh bas ek line mein kitne switches hain ka sawaal hai. Agar tumne switches ki woh line picture nahi ki, toh "256-bit register" ek spell hai, fact nahi.

Figure mein lal byte dekho: 8 switches, aur jo pattern dikhaya gaya hai woh number 20 hai. Wahi akela number baad mein "woh brightness hogi jo hum ek pixel mein add karenge."

Recall 8 bits se 256 values kyun milti hain

Har bit patterns ki count double kar deta hai. 1 bit → 2 patterns, 2 bits → 4, ... 8 bits → $2^{8} = 256$ . ✅

2. "Register" — CPU ki choti si desk

Socho ek whiteboard par jo CPU ek number likhta hai, mita ta hai, agla likhta hai. Ek scalar register mein bilkul ek hi number hota hai.

SIMD ka poora trick yeh hai: whiteboard ko itna wide banao ki usme numbers ki poori row aa sake, aur ek command ko poori row par kaam karne do.

3. "Lane" — wide desk mein ek slot

Topic ko yeh word kyun chahiye: parent kehta hai "operates on all lanes." Yahi toh poora SIMD ka waada hai. Ek instruction starting pistol chalata hai; chaaron runners ek saath aage badhte hain.

4. "Float", "double", "8-bit int" — lane mein kaisa number baithta hai

Kyun matter karta hai: format decide karta hai ki kitne lanes fit honge. Same 128-bit box, alag tenants:

Box width	Lane size	Lanes ( $w$ )
128 bits	32-bit float	4
128 bits	64-bit double	2
128 bits	8-bit uint	16

Across padho: chhota number matlab zyada lanes matlab bada speed-up. Wahi ek table explain karta hai kyun image code (8-bit pixels) 16× milta hai jabki double-precision science sirf 2× milti hai.

5. "Packed" aur "contiguous" — row kaise load hoti hai

Topic ko yeh kyun chahiye: SIMD ka single grab (movaps) tab hi kaam karta hai jab data pehle se seedhi line mein ho. Bikhra hua data pehle gather karna padta hai, jo slow hai. Yahi Cache Optimization aur Loop Vectorization ka beej hai — apna data row ki tarah arrange karo aur hardware tumhe reward dega.

6. Sigma $\sum$ — "poori list add karo"

Topic ko yeh kyun chahiye: yahi exact expression Example 2 mein dot product hai. Jab parent lane-by-lane multiply karta hai aur phir "horizontally sum" karta hai, woh literally yahi $\sum$ compute kar raha hota hai. Symbol se pehle milna zaroori hai taaki baad mein shock na lage.

Recall Sigma ke neeche aur upar

$i$ ka kya matlab hai? Neeche = counter kahan se start hota hai, upar = kahan rukta hai. Yeh kehta hai "yeh kaam har $i$ ke liye start se stop tak karo aur results add karo." ✅

7. Ceiling $⌈ ⌉$ — "hamesha upar round karo"

Topic ko yeh kyun chahiye: agar tumhare paas 10 numbers hain lekin lanes 8 ke groups mein aate hain, tumhe 2 instructions chahiye — doosra instruction tab bhi fire hoga jab usmein sirf 2 real numbers hain. "1.25 instructions" nahi ho sakta. Ceiling us leftover-group ki sacchhai pakadta hai, aur yahi wajah hai kyun parent loop remainders ke baare mein warn karta hai.

8. Speed-up $S$ — payoff number

Ab parent ke boxed result $S \approx w$ ka har symbol ek aisa symbol hai jo tum pehle hi mil chuke ho: $T$ time hai, $w$ §3 se lane count hai, aur §7 se ceiling yahi wajah hai kyun yeh approximately $w$ hai aur bilkul exactly $w$ nahi.

9. Same-instruction rule — golden constraint

Yeh constraint SIMD ko Flynn's Taxonomy mein SIMD class mein rakhti hai (ek instruction stream, kai data streams), aur ise Data Paralelism ke peeche ka hardware engine banati hai.

Prerequisite map

Left mein jo kuch bhi hai woh plain picture hai; sab kuch flow hokar right mein parent topic mein jaata hai. Agar koi bhi left-hand box fuzzy lage, aage badhne se pehle us section ko dobara padho. Yeh map Loop Vectorization, Auto-vectorization, aur Instruction-Level Parallelism ke on-ramps bhi dikhata hai — in sab mein yahi atoms reuse hote hain.

Equipment checklist

Right side cover karo aur oopar se jawab do; check karne ke liye reveal karo.

Byte kya hai, switches mein?

8 bits ka ek bundle,

2^{8} = 256

patterns mein se koi ek rakhta hai.

CPU ka sabse fast chota storage box, jo abhi kaam kar rahe numbers ko rakhta hai, bits mein width ke saath.

Lane kya hai?

Ek wide register ka ek barabar slice; har lane ek independent number rakhta hai.

128-bit register mein kitne 32-bit float lanes fit hote hain?

128/32 = 4

lanes.

128 bits mein kitne 8-bit lanes fit hote hain?

128/8 = 16

lanes.

"Packed / contiguous" ka kya matlab hai?

Numbers memory mein ek doosre ke paas hote hain aur ek hi grab mein load hote hain.

\sum_{i = 0}^{3} a_{i}

ko words mein padho.

a_{0} + a_{1} + a_{2} + a_{3}

add karo; counter

i

0 se 3 tak chalta hai.

⌈ 10/8 ⌉

kitna hota hai aur kyun?

2, kyunki ek leftover partial group ko bhi ek poora instruction chahiye.

S

kya measure karta hai aur uski ideal value kya hai?

SIMD kitni baar faster hai; ideally

S \approx w

, lane count.

SIMD har element par if/else kyun nahi chala sakta?

Ek instruction ek saath saare lanes drive karta hai — har lane ko identical operation karni padti hai.

Agla stop: Vector - SIMD instructions (SSE, AVX, NEON) — ab tumhare paas har woh symbol hai jo woh use karta hai.