Worked examples — Multicore vs manycore designs
6.1.4 · D3· Hardware › Parallelism & Multicore › Multicore vs manycore designs
Yeh page parent topic ka "boss fight" hai. Hum woh do formulas lenge jo parent ne introduce ki thi — Amdahl's Law se speedup formula aur throughput formula — aur inhe har kone mein push karenge: easy cases, broken cases, "exactly zero" wale cases, aur woh jo dekhne mein toh ek design ko favour karte lagte hain lekin secretly doosre ko karte hain.
Koi bhi number aane se pehle, chalo un do symbols ko dobara anchor karte hain jo hum baar baar use karenge, kyunki kaafi "wrong answers" inhe mix up karne se aate hain.
Yeh exact formulas hain jo hum use karenge, parent se copy ki gayi hain taaki koi bhi symbol bina earn kiye use na ho:
Do chips examples mein baar baar aayenge, toh chalo unke parameters ek baar yahan fix kar lete hain aur naam de dete hain, rather than mid-problem mein numbers sneakily daalne ke:
Scenario matrix
Is topic ke har sawaal ka jawaab inhi cells mein se kisi ek mein aata hai. Neeche ke worked examples mein label hai ki woh kaun sa cell cover karte hain, aur milke sab cells hit ho jaate hain.
| Cell | Jo "input extreme" test ho rahi hai | Yeh kya probe karta hai |
|---|---|---|
| A | (kuch bhi parallel nahi) | Serial floor — degenerate low end |
| B | (perfectly parallel) | Manycore dream — degenerate high end |
| C | , chhota | Realistic multicore |
| D | (limiting behaviour) | Amdahl's ceiling |
| E | Throughput vs latency clash | Same chips, opposite winners |
| F | Area/transistor tradeoff | Kyun do philosophies exist karti hain |
| G | Utilization collapse ( small) | Jab manycore ki flood sukh jaaye |
| H | Real-world word problem | Description se design choose karna |
| I | Exam twist (the trap) | Jahan "obvious" answer galat hota hai |
Worked examples
Example 1 — Cell A: kuch bhi parallel nahi ()
- likho. "100% serial" matlab parallel fraction hai. Yeh step kyun? English ("serial") ko us symbol mein translate karna jis par formula kaam karta hai — yahin sabse zyada errors hote hain. parallel fraction hai, toh serial-only matlab hai, nahi.
- Amdahl mein substitute karo: Yeh step kyun? term wahi jagah hai jahan appear karta hai. Agar hai, toh woh poora term gayab ho jaata hai aur invisible ho jaata hai — cores literally is problem ko touch nahi kar sakte.
- Interpret karo: matlab "exactly ek core jitna fast." Baaki 511 cores idle baithte hain. Yeh step kyun? Ek degenerate case ko name karna zaroori hai taaki aap ise live pehchan sako: dependency chains parallelism ko completely defeat karti hain.
Verify: (ek core, baseline) ko same formula mein plug karo: . Same answer jaise — confirm karta hai ki extra cores ne kuch nahi add kiya. Units: speedup dimensionless hai (times ka ratio), aur "no change" value hai. ✓
Example 2 — Cell B & D: perfect parallelism, phir limit
- confirm karo. Independent entries ⇒ zero serial fraction. Yeh step kyun? wahi ek value hai jo speedup ko bina ceiling ke grow karne deti hai — isliye ise verify karna worth it hai.
- Part (a): . Yeh step kyun? Serial term gone hone ke baad, speedup exactly ho jaata hai — linear scaling, manycore ka dream.
- Part (b), the limit: jaise , , isliye Yeh step kyun? Yeh ONLY woh hai jiske liye limit infinite hai. Yeh Cells B aur D ke beech boundary dikhata hai: perfect parallelism ki koi ceiling nahi hai; kuch bhi kam hone par hoti hai (agla example).
Verify: Reality check — parent notes mein actual A100 speedup ~4000× hai, 6912× se kam. Yeh consistent hai: hamara theoretical max hai (utilization ); real mein memory bandwidth ko 1 se neeche kheenchti hai, isliye real speedup < 6912. Model over-estimate karta hai, under-estimate nahi — sahi direction. ✓
Example 3 — Cell D: imperfect ke liye Amdahl's ceiling
-
Limit lo: Yeh step kyun? Yeh Amdahl ka sabse important consequence hai: sirf 5% serial slice aapko hamesha ke liye 20× par cap kar deta hai.
Ab neeche wali figure dekho. Har curve fixed ke liye hai jaise hum ko right ki taraf badhate hain. Blue curve pehle steeply climb karta hai, phir bend ho jaata hai aur red dashed line se par flat ho jaata hai — woh red line exactly woh hai jo humne abhi compute ki. Picture is step ka visual proof hai: chahe aap kitna bhi right jaao (zyada cores), curve apni ceiling cross nahi kar sakta.

- Ceiling ka aadha paane ke liye dhundho (): solve karo . Phir . Yeh step kyun? Yeh curve ki cruelty expose karta hai: 19 cores aapko tak pahuncha dete hain, lekin reach karne ke liye infinitely many chahiye. Figure mein yeh white dot hai par — notice karo yeh red ceiling tak sirf halfway par baitha hai, halanki hum pehle hi 19 cores spend kar chuke hain. Us dot ke right mein sab kuch diminishing returns ka region hai.
Verify: wapas plug karo: . ✓ Aur , exactly ceiling ka aadha. ✓
Example 4 — Cell C: realistic multicore, chhota
- , substitute karo: Yeh step kyun? Serial term denominator mein dominate karta hai — yeh wahi "killer" hai jo parent ne warn kiya tha. Yeh fixed rehta hai chahe aap kitne bhi cores add karo.
- Compute karo: . Yeh step kyun? Bahut chhota speedup — phir bhi multicore yahan sahi choice hai (step 3 dekho), yahi poori baat hai.
- Base core speeds compare karo. Ek REF-CPU core karta hai GIPS; ek REF-GPU core karta hai GIPS — REF-CPU core ek thread par faster hai. Kyunki is workload ka 70% ek thread par chalta hai, woh base speed dominate karta hai; modest parallel bonus pehle se hi fast core ke upar sawaar hota hai. Yeh step kyun? Speedup ek core ke relative hai; base core matter karta hai. Named REF-CPU / REF-GPU numbers use karna (vague "high IPC" ki jagah) comparison ko concrete banata hai: multicore branchy code mein isliye jeet jaata hai kyunki uska base thread ~10× quicker hai, core count ki wajah se nahi.
Verify: . ✓ Base-speed ratio . ✓ Sanity: ke saath, strictly se kam aur se zyada hona chahiye — aur hold karta hai. ✓
Example 5 — Cell E: same do chips, throughput winner flip ho jaata hai
Compute karne se pehle ek chhota unit note. (GHz mein) clock ticks per second hai; instructions per tick hai. Inhe multiply karo, "ticks" cancel ho jaate hain: ki units instructions per second hain — yeh honest per-core work rate hai, aur yahan "single-thread performance" ka yahi matlab hai. (Neeche shorthand ka matlab hai "ek core par 16 giga-instructions per second," kyunki .)
- REF-CPU throughput: GIPS. Yeh step kyun? Throughput formula ke charon factors multiply karo; GHz × IPC deta hai billions of instructions/sec per core, ×cores×U deta hai chip total.
- REF-GPU throughput: GIPS. Yeh step kyun? Same formula, ulta balance: tiny per-core numbers, bahut bada core count. Count product mein jeet jaata hai.
- Ratio: → REF-GPU throughput mein jeetta hai. Yeh step kyun? Confirm karta hai ki firehose eyedropper ko volume par beat karta hai.
- Single-thread: ek core instructions per second karta hai. REF-CPU: GIPS; REF-GPU: GIPS. Ratio → REF-CPU latency mein jeetta hai. Yeh step kyun? Flip dikhata hai: throughput loser latency winner hai. Same silicon, opposite verdicts, depending on aapne kya poochha.
Verify: ✓; ✓; ✓; ✓. Units: GIPS = giga-instructions per second (ek rate) throughput ke liye; single-thread numbers (, ) bhi GIPS hain lekin per core, isliye inhe whole-chip totals se compare mat karo — isliye do alag ratios hain. ✓
Example 6 — Cell F: transistor tradeoff, area se
- Complex cores: . Yeh step kyun? Area budget ÷ area-per-core = count. Die fixed pie hai; har mota core ek bada slice leta hai.
- Simple cores: . Yeh step kyun? Same pie, patle slices ⇒ bahut zyada unhe fit ho sakte hain.
- Ratio: . Yeh step kyun? Ratio ko die size ki zaroorat bhi nahi — yeh sirf area ratio hai. Ek mota core = pachaas patle wale. Yahi physical reason hai ki do philosophies saath exist nahi kar saktin: Power Consumption aur area ek fixed budget hai jise aap ek baar spend karte ho.
Ab us arithmetic ko neeche wali figure se compare karo. Left panel ek single die tile hai jo almost entirely ek blue core se bhara hai — multicore ka tarika, sab kuch bada aur clever hone par kharch karna. Right panel same-size tile hai (yellow "same area" arrow dekho jo dono ko bridge karta hai) jo tiny green cores ke grid se tiled hai — manycore ka tarika. Aankh ek dum woh cheez dekh leti hai jo step 3 ne prove ki: ek mota core aur pachaas patle cores same silicon occupy karte hain. Woh equal area hi woh poori wajah hai "aap dono nahi rakh sakte."

Verify: ✓; ✓; ✓. Units: mm² / mm² = dimensionless count. ✓
Example 7 — Cell G: utilization collapse (manycore ki flood sukh jaati hai)
- ke saath REF-GPU throughput recompute karo: GIPS. Yeh step kyun? sab kuch linearly multiply karta hai — divergence (dekho SIMD vs MIMD) manycore ki kryptonite hai kyunki iski cores instruction streams share karti hain aur saath mein stall karti hain.
- Compare karo: → REF-CPU ab throughput mein bhi jeet jaata hai. Yeh step kyun? Yeh manycore side ka degenerate case hai: jab workload irregular ho, uska numerical advantage gayab ho jaata hai. Yeh sawaal ka jawaab deta hai "firehose eyedropper se kab haarta hai?" — jab firehose 90% hawa ho.
- Break-even solve karo (part b): REF-GPU throughput ko REF-CPU ke 115.2 GIPS ke barabar set karo aur ke liye solve karo: Yeh step kyun? Yeh vague chinta "manycore kabhi kabhi haarti hai" ko ek exact, predictable threshold mein convert karta hai. se neeche REF-GPU, REF-CPU se peeche pad jaata hai; usse upar REF-GPU jeetta hai. Ab aap workload regularity se akele winner forecast kar sakte ho, bina poori calculation dobara chalaye — is cell mein sabse useful number.
Verify: ✓; ✓; ✓ — aur indeed normal (Example 5) se kaafi upar hai, consistent REF-GPU ke wahan jeetne ke saath, jabki se neeche hai, consistent iske yahan haarne ke saath. ✓
Example 8 — Cell H: real-world word problem
- Database classify karo. Query planning sequential hai with unpredictable branches; index traversal pointer chasing hai; locks serial critical sections hain ⇒ low , irregular. → multicore. Yeh step kyun? Low parallel fraction + branchy control flow exactly Cell A/C territory hai jahan core count help nahi kar sakta aur fast single-thread (Thread-Level Parallelism with few strong threads) matter karta hai.
- Training loop classify karo. Dense matmul ⇒ , regular, Cache Coherence-light, bandwidth-bound. → manycore. Yeh step kyun? Cell B hai — wahi regime jahan thousands of cores linearly pay off karte hain.
- Decision: database → multicore CPU; training → manycore GPU. Agar exactly ek kharidna ho, toh decide karo ki kaun si service revenue ki bottleneck hai: agar latency-per-transaction woh cheez hai jo customers pay karte hain, toh multicore CPU khareedo aur occasional training ke liye GPU time rent karo; agar product hi trained model hai, toh manycore GPU khareedo aur database existing host CPU par chalao. Genuinely sahi architecture, agarchi, yeh hai ki dono rakho aur har workload ko us chip par route karo jo use suit kare — yeh exactly Heterogeneous Computing design pattern hai. Yeh step kyun? Yeh reader ko force karta hai notice karne ke liye ki "kaun better hai" hamesha workload-relative hota hai; koi universal winner nahi hai, aur real systems yeh dilemma dono use karke resolve karte hain.
Verify: Example 4 (branchy 30%-parallel → multicore , base-speed matters) aur Example 2 ( matmul → manycore ) se cross-check karo. Dono worked examples is classification se agree karte hain. ✓
Example 9 — Cell I: exam trap
- Trap spot karo: hai, nahi. Naive reader core count se multiply kar deta hai. Yeh step kyun? "90% parallel" word deliberately 100% ke kareeb hai taaki aapko linear scaling mein tempt kare. Sirf linearly scale karta hai (Example 2).
- Sahi se compute karo: . Yeh step kyun? Serial term include karo — wahi term jise trap aapko bhulwana chahta hai.
- Result: . Ceiling () sirf hai. Yeh step kyun? , ke kareeb bhi nahi. Answer: FALSE. 1000 cores aapko ek bekar ceiling ka 99% dilate hain.
Verify: ✓; ceiling ✓; aur (limit se neeche hona chahiye) ✓. ✓
Recall Quick self-test
512 cores par 100% serial task speedup kya deta hai? ::: Exactly — cores useless hain (Cell A). ke liye speedup ceiling? ::: (Cell D). Ek core kitne cores ke barabar hai? ::: (Cell F). Kis utilization ke neeche 512-core REF-GPU, 115.2 GIPS REF-CPU se haar jaata hai? ::: (Cell G). "90% parallel on 1000 cores ≈ 1000×" — true ya false? ::: False, yeh hai, ceiling (Cell I).