5.4.11 · D3Memory Hierarchy & Caches

Worked examples — Virtual memory and paging

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This page is the "no surprises" drill. The parent note taught you the machinery of address translation; here we hit every kind of number that machinery can be fed — clean cases, edge cases, degenerate cases, and the sneaky exam twists — so that when one shows up on paper you've already seen its twin.

Everything here rests on three ideas from the parent that we will re-use constantly, so let's re-anchor them in one breath (no new symbol without a picture):

Figure — Virtual memory and paging

Look at the figure: an address is a ruler. The red line at bit is the cut. Everything left of the cut is the VPN (it gets replaced), everything right stays glued on unchanged. Nothing in this page ever moves that red line except by changing the page size. Keep that picture in your head.


The scenario matrix

Every problem this topic can throw is one (or a combo) of these cells. We will hit all of them.

Cell What makes it tricky Covered by
A. Clean split plain hex, digits line up Ex 1
B. Non-nibble page size not a multiple of 4, so hex digits split mid-digit Ex 2
C. Offset = 0 (page boundary) address sits exactly on a page start Ex 3
D. Offset = max (last byte of page) address is the very last byte before rollover Ex 3
E. Reverse direction given PA, recover VA (inverse map) Ex 4
F. Table-size scaling how RAM for tables grows with VA bits / entry size Ex 5
G. Multi-level walk VPN itself splits into index levels Ex 6
H. Performance / EAT limiting behaviour as hit ratio and Ex 7
I. Word problem swap/disk timing, "is this a page fault?" Ex 8
J. Degenerate / trap invalid VPN, unmapped page, offset overflow Ex 9

If a cell isn't in an example below, it's a bug in this page. Let's go.


Cell A — the clean split


Cell B — the page size that splits a hex digit

Real exams love a page size like , where is not a multiple of 4. Now the cut runs through the middle of a hex digit, and "keep last few hex digits" silently fails. You must fall back to binary.


Cells C & D — offset at both extremes (page boundaries)

The two most misread inputs are the first byte of a page (offset ) and the last byte (offset ). Let's do both at once and watch what happens if you step one byte past the last.

Figure — Virtual memory and paging

The figure shows it: virtual pages 8 and 9 sit side by side, but their frames (3 and, say, 7) are scattered in physical RAM. The page boundary is a hard wall — cross it and you re-consult the table.


Cell E — running the map backwards

Given a physical address, which virtual address produced it? The offset is trivial (unchanged). For the page part you invert the table: find the VPN whose entry is this PFN.


Cell F — how the table cost scales


Cell G — the multi-level walk

The fix for Cell F: split the VPN itself into index pieces, one per table level, and only build the sub-tables actually used.


Cell H — performance at the limits

Figure — Virtual memory and paging

The figure plots EAT versus hit ratio: a straight line from to . The steepness ( per unit of hit ratio) is the miss penalty. Real TLBs live at the far-right (), hugging .


Cell I — the word problem (swap timing)


Cell J — degenerate & trap inputs


Recall

Recall Which cell is this? (cover the answers)
  • Page size , VA : what's the offset? ::: (Cell B — mask , non-nibble).
  • PA sits exactly on a frame boundary. What's its offset? ::: (Cell C).
  • Given a PA, is recovering the VA always unique? ::: Only within one process's page table (Cell E).
  • 48-bit VA, 4 KiB pages, 8-byte entries — flat table size? ::: , hence multi-level (Cell F).
  • Two-level walk: memory accesses per translation on a TLB miss? ::: 3 (2 table + 1 data) (Cell G).
  • EAT as with ? ::: (Cell H).
  • Valid bit is 0 and the page was never allocated — what fires? ::: A segmentation fault (Cell J).