Cache line size and tags: Question bank — Hinglish deep dive

5.4.4 · D5 · Hardware › Memory Hierarchy & Caches › Cache line size and tags

Traps se pehle, ek picture dekho jo poora mental model dimag mein fix kar deti hai:

Upar ka address bar left-to-right teen coloured chunks mein slice hua hai. Left pe magenta Tag sabse chauda hai — yeh sab kuch hai jo lookup ke liye use nahi hota. Beech mein violet Index cache grid ki ek row ko point karta hai. Right pe orange Offset us fetch ki gayi row ke andar ek byte ko point karta hai. Notice karo ki offset low (right) end pe hai: consecutive byte addresses sirf wahan differ karte hain, isliye poori line ek tag+index share karti hai — yahi spatial locality visible hoti hai.

Ek quick shared vocabulary taaki har answer samajh aaye (sab parent mein build hain):

True or false — justify karo

True or false: Byte X pe cache miss hone ka matlab hai byte X+1 bhi guaranteed miss hai.

False. X aur X+1 usually same line mein hote hain, toh jab X ki line fetch ho jaaye, X+1 hit hoga — isliye hi lines multi-byte hoti hain (dekho 3.1.04-Spatial-locality).

True or false: Offset bits ko ek stored offset ke against compare kiya jaata hai hit detect karne ke liye.

False. Sirf tag compare hota hai; offset kabhi hit/miss mein participate nahi karta — yeh bas hit ke baad return karne ke liye byte select karta hai.

True or false: Do alag addresses same index share kar sakte hain phir bhi cache mein kabhi collide nahi karenge.

True. Set-associative cache mein same set multiple ways hold karta hai, isliye equal index wale do blocks coexist kar sakte hain jab tak ek free way (ya victim) available ho.

True or false: Cache size double karne par line size fixed rakhte hue tag bits ki sankhya badhti hai.

False. Capacity double karne se ek index bit badhta hai, isliye tag bits ek kam ho jaate hain — ab address ka zyada hissa "which slot" ke liye use hota hai toh blocks distinguish karne ke liye kam bits chahiye.

True or false: Valid bit sirf write-back caches ke liye zaroori hota hai.

False. Har cache ko valid bit chahiye yeh jaanne ke liye ki slot mein real data hai ya power-on ka leftover garbage; dirty bit woh hai jo write-back ke liye specific hai (dekho 5.4.08-Write-policies).

True or false: Cache lines badi karna hamesha miss rate kam karta hai.

False. Ek sweet spot ke baad tum aisi bytes fetch karte ho jo kabhi use nahi hoti aur line count kam ho jaata hai, conflict misses aur miss penalty badh jaati hai — typical general-purpose workloads mein benchmarks (jaise SPEC) ke across balance point usually 64 bytes ke paas hota hai, lekin streaming ya pointer-chasing workloads alag sizes prefer karte hain.

True or false: Tag bits address ki fixed property hain, cache se independent.

False. Tag/index/offset ke beech split point cache ki size, line size, aur associativity se decide hota hai — same address ke alag-alag caches mein alag-alag tags hote hain.

True or false: Fixed cache aur line size ke liye, direct-mapped aur 2-way set-associative dono same number of offset bits use karte hain.

True. Offset sirf line size pe depend karta hai (

b = lo g_{2} L

); associativity index/tag boundary change karta hai, offset nahi.

Error pakdo

"64-byte lines ko 7 offset bits chahiye kyunki

64 = 2^{7}

." — kya galat hai?

64 = 2^{6}

hai,

2^{7}

nahi, isliye 6 offset bits hain. Bit count ke liye value nahi, exponent dena hota hai.

"Ek 32 KiB, 64-byte-line, direct-mapped cache mein 32768/64 = 512 sets hain, isliye isko 512 index bits chahiye." — slip pakdo.

Tumhe

lo g_{2} 512 = 9

index bits chahiye, 512 nahi. Index bits yeh count karte hain ki kitne bits slots ko address karte hain, slot count khud nahi.

"Ek byte find karne ke liye hardware pehle tag use karta hai slot pick karne ke liye, phir index data confirm karne ke liye." — roles theek karo.

Ulta hai. Index slot pick karta hai (fast, direct lookup), phir Tag confirm karta hai ki block sahi hai.

"Set-associative caches tag field drop kar dete hain kyunki multiple blocks ek set share karte hain." — error kya hai?

Woh tag rakhte hain aur asliyat mein unhe zyada zaroorat hoti hai — set mein har way apna tag store karta hai taaki comparators bata sakein ki kaun sa way (agar koi ho) tumhara block hold karta hai.

"Line size 64 se 32 bytes tak half karne se har line pe tag overhead kam hoti hai." — galti kahan hai?

Yeh overhead badhata hai. Chhoti lines matlab zyada lines total, har ek apna (ab bada) tag carry karta hai, isliye capacity ke fraction ke roop mein metadata badh jaati hai.

"Kyunki offset low bits mein hai, jo byte chahiye usse change karne par index change ho jaata hai." — confusion pakdo.

Sirf tab jab tum line boundary cross karo. Ek line ke andar index aur tag identical hote hain; sirf offset vary karta hai, aur yahi neighbors ko group karne ka poora point hai.

"Hit ke liye tag match hona chahiye AUR valid bit 0 hona chahiye." — logic theek karo.

Hit ke liye tag match hona chahiye AUR valid bit 1 hona chahiye (line real data hold karti hai). Valid = 0 matlab slot empty hai, miss force hoti hai.

Why questions

Offset address ke low bits mein kyun hota hai high bits ki jagah?

Kyunki consecutive byte addresses sirf apne low bits mein differ karte hain, isliye offset ko low rakhne se ek poora contiguous block ek tag+index share karta hai — yahi spatial locality ko cache hits mein translate karti hai.

Index par trust karne ki bajaye tag compare kyun karein?

Bahut se memory blocks same index pe map hote hain (index sirf kuch bits ka hai), isliye tag woh collision check hai jo answer deta hai "kya yeh woh block hai jo maine store kiya, ya koi aur jo sirf slot share karta hai?"

Line size hamesha power of two kyun hoti hai?

Taaki byte offset exact whole number of bits ho (

b = lo g_{2} L

); non-power-of-two address split misaligned kar deta aur clean bit-slice ki jagah division ki zaroorat padti.

Badi lines total tag storage kyun kam karti hain jabke har tag wider hota hai?

Fewer lines dominate karta hai:

L

double karne par line count half ho jaata hai jabke har tag mein sirf ek bit add hoti hai, isliye total metadata bytes kam ho jaate hain — zyada data har tag ko amortize karta hai.

4 KiB cache mein zyada tag bits kyun ho sakte hain 16 KiB cache se jab line size same ho?

Chhoti cache mein fewer slots hain, isliye fewer index bits, isliye address ka zyada hissa tag ki tarah kaam karna padta hai — tag width badhti hai jab index width ghatti hai.

CPU exactly woh ek byte kyun nahi fetch karta jo maanga gaya?

Memory bus aur DRAM burst wide transfers ke liye optimized hain, aur locality ka matlab hai neighbors jaldi chahiye honge — poori line fetch karna ek slow access pay karta hai lekin bahut se future requests fast serve karta hai.

Edge cases

Index bits = 0 hone par (fully associative cache) tag bits kya hote hain?

Koi index field nahi hone par,

t = N - b

— har non-offset bit tag ban jaata hai, aur hardware ko woh tag har line ke against parallel compare karna padta hai.

Agar line size exactly 1 byte ho toh offset field ka kya hoga?

b = lo g_{2} 1 = 0

, isliye koi offset nahi — har byte apni line hai, maximum line count milti hai lekin zero spatial-locality benefit aur huge tag overhead hota hai.

Agar poora cache ek single line hai (

C = L

), toh kitne index bits hain?

Zero index bits: ek slot matlab koi selection zaroorat nahi, isliye address sirf tag + offset hai — effectively ek trivial fully-associative cache of size one.

Ek access offset = 0 pe land karta hai aur requested data agली line mein bhi jaata hai. Kya hona chahiye?

Access line boundary cross karta hai, isliye cache do lookups resolve karta hai (do index/tag pairs) — ek har line ke liye — yahi wajah hai ki unaligned accesses extra cost kar sakte hain.

Power-on ke baad, har tag comparison luck se "match" karta hai. Phir bhi yeh miss kyun hai?

Valid bit uninitialized slots ke liye 0 hota hai, isliye hardware accidental tag match ko ignore karta hai aur miss force karta hai — valid comparison ko gate karta hai.

Do addresses sirf apne tag bits mein differ karte hain. Kya woh same slot pe map karte hain?

Haan — identical index aur offset matlab same slot, isliye woh conflict karte hain: sirf ek slot pe ek waqt reh sakta hai, conflict misses cause karta hai (dekho 5.4.05-Cache-miss-types).

Agar associativity

A

total lines ki sankhya ke barabar ho, toh index kya degenerate ho jaata hai?

Sets

= C / (L \cdot A) = 1

, isliye index bits

= 0

— cache fully associative ban jaata hai aur index field tag mein ghus jaata hai.

Connections

Cache line size and tags — parent note jisko ye traps stress-test karte hain.
5.4.01-Cache-fundamentals — poore tag/index/offset model ki foundation.
5.4.02-Direct-mapped-caches — jahan one-tag-per-slot comparison rehta hai.
5.4.03-Set-associative-caches — kyun index ek set index ban jaata hai aur tags multiply karte hain.
5.4.05-Cache-miss-types — edge cases mein referenced conflict vs. compulsory misses.
5.4.08-Write-policies — valid-bit traps se dirty bit distinction.
6.2.01-Virtual-memory-pages — page tables same field-split idea reuse karte hain.
3.1.04-Spatial-locality — wajah ki lines wide hoti hain, "why" section ki neenv.
Hinglish version — same ideas Hinglish mein.