5.4.4 · D1Memory Hierarchy & Caches

Foundations — Cache line size and tags

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This page assumes you know nothing. We build every word, symbol, and picture the parent note 5.4.4 leans on, in an order where each idea rests on the one before it.


0. What is a bit? (the atom of everything below)

Picture a row of light switches. Each switch is a bit. If I have 3 switches, how many different patterns can they show? Switch each on or off independently:

Figure — Cache line size and tags

Look at the red count on the right: 3 switches give patterns. In general:

Why the topic needs this. A memory address is a row of bits. The whole game of caches is: "how many bits do I spend on each job?" — and "how many patterns can these bits name?" is exactly .


1. Powers of two and (counting the switches)

We just saw . The exponent notation means "multiply 2 by itself times".

Now the reverse question. Suppose I have 64 patterns and I ask: how many switches did that take? The answer is 6, because . The tool that answers "which exponent produces this number?" is .


2. Byte, and the units KiB (grouping the switches)

Memory sizes get large, so we group bytes:


3. Hexadecimal (a shorthand for long bit rows)

Writing a 32-bit address as 32 zeros and ones is painful. Hex packs 4 bits into one symbol, because 4 bits give patterns and hex has exactly 16 digits: 0 1 2 3 4 5 6 7 8 9 A B C D E F.

Figure — Cache line size and tags

The 0x prefix just flags "this is hex". So 0x2 means the value 2; 0xA9 means .

Why the topic needs this. Addresses are shown in hex everywhere in the parent (tag 0x2, index 0xA9). Hex is only a rewriting of the bit row — no new information, just fewer characters.


4. Memory address (a numbered slot in the big book)

For : billion addressable bytes.

Why the topic needs this. The entire parent page is about cutting one address into three fields. If you don't know an address is just a row of bits, the cutting has no meaning.


5. Cache line / block (the chunk we copy)

Figure — Cache line size and tags

The red bracket shows one line: the CPU asked for the byte marked with the arrow, but the cache grabbed the whole bracketed run. It bets you'll want the neighbours next — that bet is spatial locality.

Why the topic needs this. The line is the unit everything measures against: offset bits = "which byte inside the line", and line count drives the index bits.


6. The three address fields (putting it together)

Now every prerequisite is in hand, the parent's central picture makes full sense. Split the address bits, from the top (high bits) down:

Figure — Cache line size and tags

Prerequisite map

Bit: a 0 or 1 switch

n bits give 2 to the n patterns

log base 2 counts the bits

Byte is 8 bits and KiB is 1024 bytes

Hex packs 4 bits per digit

Memory address is N bits

Offset bits equal log2 of line size

Index bits equal log2 of line count

Cache line is L neighbour bytes

Split address into Tag Index Offset

Cache line size and tags 5.4.4


Equipment checklist

You are ready for the parent note when you can answer each of these without peeking:

How many patterns can 6 bits represent?
What does equal, and why?
, because
How many bytes are in KiB?
bytes, which is
Why does hex pack exactly 4 bits per digit?
Because and hex has 16 digits (, )
What is a cache line, in one sentence?
A fixed run of neighbouring bytes copied together from memory as one unit
Which field is the lowest bits of an address, and what does it pick?
The offset; it picks the byte inside the line
Given line size , how many offset bits ?
Given cache size and line size (direct-mapped), how many index bits ?
Given an -bit address, how many tag bits ?

Connections

  • 5.4.01-Cache-fundamentals — why we bother caching at all
  • 5.4.02-Direct-mapped-caches — the first cache that uses these three fields directly
  • 3.1.04-Spatial-locality — the reason a line holds many bytes
  • 6.2.01-Virtual-memory-pages — the same "split the address" trick, applied to pages
  • Yeh foundation Hinglish mein →