Intuition The one core ideaA pipeline runs several instructions at once, so they finish out of order — but a program is written to run one instruction at a time, fully, in order. A precise exception is the trick that lets fast overlapping hardware freeze itself so it looks exactly like a slow one-at-a-time machine at the moment something goes wrong.
This page assumes you know nothing . Before we can talk about "precise exceptions" (the parent topic ), we must build every word and symbol that topic throws at you. We go in order — each idea uses only ideas already defined.
A single command the processor obeys, like ==ADD R 1 , R 2 , R 3 R 2 R 3 R 1 R 1 , R 2 , R 3 registers — tiny named storage boxes inside the processor.
Think of registers as a row of labelled cups. An instruction pours numbers between cups. A program is a stack of instruction cards you obey top to bottom, one at a time.
We will call the instructions I 1 , I 2 , I 3 , … position in program order (the order they are written). I 3 I 2 I 4
Definition Architectural stateThe values the program is allowed to see : all registers (R 1 , R 2 , … official score of the machine. Anything a program can read or is guaranteed by the manual counts as architectural state.
Intuition Why this word existsHardware secretly juggles half-finished results in hidden scratch areas. Those hidden scratch values are not architectural — the program can't see them. Only when a result is officially written into a register or memory does architectural state change. This distinction is the whole game: precise exceptions work by controlling when the official score updates.
Look at figure s01: the blue cups are architectural state (visible), the grey scratch pad holds temporary results the program cannot see. An instruction only "counts" the instant its result crosses from grey to blue.
Executing one instruction is not instant. We split the work into 5 stages , each done by a different piece of hardware:
Definition The 5 pipeline stages
IF (Instruction Fetch): read the instruction card from memory.ID (Instruction Decode): figure out what it says, read source registers.EX (Execute): do the arithmetic (add, divide, compute an address).MEM (Memory): read or write data memory, if needed.WB (Write Back): write the final result into the destination register — this is the only stage that changes architectural state.
I 'll I nspect, EX ecute, MEM orise, then W rite B ack — IF, ID, EX, MEM, WB.
Notice: WB is last, and WB is where the "official score" moves. Every mechanism in the parent note is really about controlling WB.
Prerequisite depth on stages lives in 5.2.1-Pipelining-basics .
Intuition The laundry pictureOne washer, one dryer, one folder. If you wash, dry, fold one load fully before starting the next, the dryer sits idle while you wash. Instead, start washing load 2 the moment load 1 moves to the dryer. Now all machines are busy — that's pipelining.
Figure s02 is the core diagram of the whole subject. Time runs left to right. Each row is an instruction; each coloured block is a stage. Read a vertical slice (one clock cycle) and you see five different instructions in five different stages simultaneously .
One tick of the processor's clock. In each cycle every stage does one step and hands its result to the next stage. We label cycles Cycle 1, Cycle 2, ...
Now stare at the vertical dashed line marked Cycle 5 in s02:
This is exactly the snapshot the parent note uses. Everything after this is: what happens if I 3
An unexpected condition that stops an instruction from completing normally, forcing the processor to jump to special rescue code. Examples: dividing by zero, accessing a memory page that isn't loaded (a page fault , see 7.2.5-Virtual-memory-exceptions ), or an illegal opcode the machine doesn't recognise.
An instruction raises its hand mid-stage and says "I can't finish — help." The processor must pause the program, run a helper routine (the handler ), then maybe resume. The full machinery of raising and catching these events is defined by the instruction set architecture .
Definition Exception handlerA block of operating-system code that runs when an exception fires . It inspects the machine, tries to fix the problem (e.g. load the missing page from disk), then either resumes the program or kills it.
For the handler to do its job it must see a clean, believable machine — as if the program had run one instruction at a time and stopped exactly at the culprit. Producing that clean view is the definition of precise .
Definition PC — Program CounterA register holding the address of the current instruction — a bookmark pointing at which card we're on. After each instruction it normally advances to the next.
Definition EPC — Exception Program CounterA special register that saves the PC of the faulting instruction when an exception fires. It's the "you were here" sticky note so the handler knows where the fault happened and where to resume.
Intuition Why two bookmarks?The moment we jump to the handler, the PC gets overwritten with the handler's address. If we didn't copy the old value into EPC first, we'd lose the crime scene. EPC is the backup bookmark.
Now we can finally state the topic precisely.
Definition Precise exceptionAn exception is precise if, at the moment the handler runs:
every instruction before the faulting one is fully complete (its WB happened),
the faulting instruction and every instruction after it have changed no architectural state, and
EPC points at exactly the faulting instruction.
Figure s03 shows the target state after I 3 green instructions (I 1 , I 2 red ones (I 3 , I 4 , I 5 That clean line is precision.
Common mistake The trap pipelining setsLook back at the Cycle-5 snapshot. I 1 I 4 , I 5 out-of-order completion : younger instructions have made progress before an older one finished. If we just freeze right now, we get a straddling line — some later work done, some earlier work not — which is imprecise . The whole topic exists to fix this.
NOP = "No OPeration" — an instruction that does nothing. Flushing an instruction means converting it into a bubble so it can never reach WB and never touch architectural state.
Turning I 4 I 5
Definition Out-of-order (OoO) executionLetting instructions execute (do their EX work) as soon as their inputs are ready, not strictly in program order — for speed. See 6.3.4-Reorder-buffer-in-superscalar .
Definition Reorder Buffer (ROB)A waiting line that holds finished results in program order and only releases (commits ) them to architectural state from the front. Execution can be chaotic; commitment is strictly ordered.
The single moment a result moves from the ROB (hidden) into architectural state (official) — the grey-to-blue crossing from figure s01. Because commit happens in program order, an exception caught at commit is automatically precise.
Definition Speculation bitA flag marking an instruction as "fetched on a guess" — e.g. fetched after a branch before we knew which way the branch goes (see 5.2.11-Branch-prediction ). If the guess was wrong, we discard the instruction and any exception it raised , because it was never really supposed to run.
Data flowing between overlapping instructions before WB is handled by forwarding — mentioned so you know where those hidden scratch values come from.
Instruction and program order
Five stages IF ID EX MEM WB
Out of order completion problem
Handler needs clean state
Precise exceptions in pipelines
Every box is a term you now own. The parent note simply combines them.
Cover the right side and test yourself. If any answer surprises you, reread that section.
What does the subscript in I 3 Its position in program order — I 3
Which single pipeline stage changes architectural state? WB (Write Back) — nothing is official until WB.
Define architectural state in one line. The registers and memory the program is allowed to see; the "official score."
Why do overlapping pipeline stages threaten precision? Out-of-order completion — a younger instruction can finish before an older one, giving a straddling done/not-done line.
What are the three guarantees of a precise exception? Earlier instructions fully done, faulting-and-later change nothing, EPC points at the culprit.
What does EPC store and why? The PC of the faulting instruction, so we know the crime scene and where to resume after the handler.
What is a bubble / NOP used for here? An eraser — flushing an instruction to a NOP so it reaches WB harmlessly, changing no state.
What is "commit" in a Reorder Buffer? The in-order moment a result moves from the hidden ROB into official architectural state.
Why does a speculation bit let us ignore some faults? A wrongly-guessed instruction should never have run, so its exception is discarded on flush.
