5.2.12 · D1Precise exceptions in pipelines
Ek pipeline ek saath kai instructions chalata hai, isliye wo out of order khatam hoti hain — lekin ek program likha jaata hai ek instruction ek baar, poori tarah se, order mein chalane ke liye. Ek precise exception woh trick hai jo fast overlapping hardware ko freeze karti hai taaki jab kuch galat ho, toh woh bilkul ek-ek karke chalne wali slow machine jaisi lagey .
Is page par yeh maana jaata hai ki aapko kuch nahi pata . Isse pehle ki hum "precise exceptions" ki baat karein (the parent topic ), hume har woh word aur symbol banana hoga jo woh topic aap par phenkhta hai. Hum order mein jaenge — har idea sirf pehle se define kiye gaye ideas use karta hai.
Ek single command jise processor maanta hai, jaise ==ADD R 1 , R 2 , R 3 R 2 R 3 R 1 R 1 , R 2 , R 3 registers hain — processor ke andar chhote named storage boxes.
Registers ko labels wale cups ki ek row ki tarah socho. Ek instruction cups ke beech numbers pour karta hai. Ek program ek instruction cards ka stack hai jise tum upar se neeche, ek ek karke maante ho.
Hum instructions ko I 1 , I 2 , I 3 , … program order mein position hai (jis order mein likhe gaye hain). I 3 I 2 I 4
Definition Architectural stateWoh values jo program ko dekhne ki ijazat hai: saare registers (R 1 , R 2 , … official score hai. Jo bhi ek program padh sakta hai ya manual guarantee karta hai woh architectural state mein count hota hai.
Intuition Yeh word kyun exist karta haiHardware chhupakar half-finished results ko hidden scratch areas mein juggle karta hai. Woh hidden scratch values architectural nahi hain — program unhe dekh nahi sakta. Sirf jab ek result officially ek register ya memory mein likha jaata hai tabhi architectural state change hoti hai. Yahi distinction poora game hai: precise exceptions kaam karte hain kab official score update hota hai yeh control karke.
Figure s01 dekho: blue cups architectural state hain (visible), grey scratch pad mein temporary results hain jo program nahi dekh sakta. Ek instruction tabhi "count" hota hai jis pal uska result grey se blue mein cross karta hai.
Ek instruction execute karna instant nahi hota. Hum kaam ko 5 stages mein todte hain, har ek alag hardware piece karta hai:
Definition 5 pipeline stages
IF (Instruction Fetch): instruction card ko memory se padho.ID (Instruction Decode): pata lagao woh kya kehta hai, source registers padho.EX (Execute): arithmetic karo (add, divide, address compute karo).MEM (Memory): data memory padho ya likho, agar zaroorat ho.WB (Write Back): final result ko destination register mein likho — yeh woh akela stage hai jo architectural state change karta hai.
I 'll I nspect, EX ecute, MEM orise, then W rite B ack — IF, ID, EX, MEM, WB.
Notice karo: WB last hai, aur WB wahi hai jahan "official score" move hota hai. Parent note ka har mechanism really WB ko control karne ke baare mein hai.
Stages par prerequisite depth 5.2.1-Pipelining-basics mein hai.
Intuition Laundry pictureEk washer, ek dryer, ek folder. Agar tum ek load fully wash, dry, fold karo agla shuru karne se pehle, dryer idle baitha rehta hai jab tum wash karte ho. Iske bajaye, load 2 wash karna shuru karo jis pal load 1 dryer mein jaaye. Ab saari machines busy hain — yahi pipelining hai.
Figure s02 poore subject ka core diagram hai. Time left se right chalti hai. Har row ek instruction hai; har coloured block ek stage hai. Ek vertical slice (ek clock cycle) padho aur tum paanch alag instructions ko paanch alag stages mein simultaneously dekhte ho.
Processor ki clock ki ek tick. Har cycle mein har stage ek step karta hai aur apna result agle stage ko deta hai. Hum cycles ko Cycle 1, Cycle 2, ... label karte hain.
Ab s02 mein Cycle 5 marked vertical dashed line ko dekho:
Yahi woh snapshot hai jo parent note use karta hai. Is ke baad sab kuch yeh hai: kya hoga agar I 3
Ek unexpected condition jo ek instruction ko normally complete karne se rokti hai, processor ko special rescue code mein jump karne par majboor karti hai. Examples: zero se divide karna, ek memory page access karna jo loaded nahi hai (ek page fault , dekho 7.2.5-Virtual-memory-exceptions ), ya ek illegal opcode jo machine nahi pehchaanti.
Ek instruction mid-stage mein haath uthata hai aur kehta hai "main khatam nahi kar sakta — help karo." Processor ko program pause karna hoga, ek helper routine (handler ) chalani hogi, phir shayad resume karna hoga. In events ko raise aur catch karne ki poori machinery instruction set architecture define karta hai.
Definition Exception handlerOperating-system code ka ek block jo tab chalta hai jab exception fire ho . Woh machine inspect karta hai, problem theek karne ki koshish karta hai (jaise missing page disk se load karna), phir ya toh program resume karta hai ya kill karta hai.
Handler apna kaam karne ke liye ek clean, believable machine dekhna chahta hai — jaise program ek ek instruction chalata gaya ho aur exactly culprit par ruka ho. Woh clean view produce karna hi precise ki definition hai.
Definition PC — Program CounterEk register jo current instruction ka address rakhta hai — ek bookmark jo point karta hai ki hum kaunsi card par hain. Har instruction ke baad yeh normally agla wala advance hota hai.
Definition EPC — Exception Program CounterEk special register jo exception fire hone par faulting instruction ka PC save karta hai. Yeh woh "you were here" sticky note hai taaki handler ko pata ho fault kahan hua aur handler ke baad resume kahan karna hai.
Intuition Do bookmarks kyun?Jis pal hum handler mein jump karte hain, PC handler ke address se overwrite ho jaata hai. Agar hum purani value pehle EPC mein copy na karte, toh hum crime scene kho dete. EPC backup bookmark hai.
Ab hum finally topic precisely state kar sakte hain.
Definition Precise exceptionEk exception precise hai agar, jis waqt handler chale:
faulting wale se pehle ka har instruction poora complete ho (uska WB hua ho),
faulting instruction aur uske baad ke har instruction ne koi architectural state change na ki ho, aur
EPC exactly faulting instruction par point kare.
Figure s03 mein I 3 Green instructions (I 1 , I 2 Red wale (I 3 , I 4 , I 5 Wahi clean line precision hai.
Common mistake Woh trap jo pipelining set karta haiCycle-5 snapshot wapas dekho. I 1 I 4 , I 5 out-of-order completion hai: younger instructions ne progress ki pehle ek older one khatam hote. Agar hum abhi sirf freeze kar dein, toh hume ek straddling line milegi — kuch baad ka kaam hua, kuch pehle ka nahi — jo imprecise hai. Poora topic isi ko theek karne ke liye exist karta hai.
NOP = "No OPeration" — ek instruction jo kuch nahi karta. Ek instruction ko flush karna matlab hai usse bubble mein convert karna taaki woh kabhi WB tak na pahunche aur kabhi architectural state na chhuye.
I 4 I 5
Definition Out-of-order (OoO) executionInstructions ko execute (apna EX kaam) karne dena jaise hi unke inputs ready hon, strictly program order mein nahi — speed ke liye. Dekho 6.3.4-Reorder-buffer-in-superscalar .
Definition Reorder Buffer (ROB)Ek waiting line jo finished results ko program order mein rakhti hai aur unhe front se architectural state mein sirf commit karti hai. Execution chaotic ho sakta hai; commitment strictly ordered hoti hai.
Woh single moment jab ek result ROB (hidden) se official architectural state (official) mein move hota hai — figure s01 se grey-to-blue crossing. Kyunki commit program order mein hota hai, commit par pakda gaya ek exception automatically precise hota hai.
Definition Speculation bitEk flag jo ek instruction ko "guess par fetch kiya gaya" mark karta hai — jaise branch ke baad fetch kiya gaya pehle yeh jaane ki branch kaunsi taraf jaayegi (dekho 5.2.11-Branch-prediction ). Agar guess galat tha, toh hum instruction discard karte hain aur koi bhi exception jo usne raise kiya , kyunki woh kabhi really chalni hi nahi chahiye thi.
Overlapping instructions ke beech WB se pehle flow hone wala data forwarding se handle hota hai — yahan mention kiya taaki aapko pata ho woh hidden scratch values kahan se aati hain.
Instruction and program order
Five stages IF ID EX MEM WB
Out of order completion problem
Handler needs clean state
Precise exceptions in pipelines
Har box ek term hai jo ab aapke paas hai. Parent note simply unhe combine karta hai.
Right side cover karo aur khud se test karo. Agar koi bhi jawab surprise kare, woh section dobara padho.
I 3 Program order mein uski position — I 3
Kaunsa single pipeline stage architectural state change karta hai? WB (Write Back) — kuch bhi official nahi hota WB tak.
Architectural state ko ek line mein define karo. Registers aur memory jo program dekhne ki ijazat rakhta hai; "official score."
Overlapping pipeline stages precision ko kyun threaten karte hain? Out-of-order completion — ek younger instruction ek older se pehle khatam ho sakti hai, ek straddling done/not-done line deti hai.
Precise exception ki teen guarantees kya hain? Earlier instructions fully done, faulting-aur-baad waale kuch nahi change karte, EPC culprit par point karta hai.
EPC kya store karta hai aur kyun? Faulting instruction ka PC, taaki hume crime scene pata ho aur handler ke baad resume kahan karna hai.
Bubble / NOP yahan kis liye use hota hai? Ek eraser — ek instruction ko NOP mein flush karna taaki woh harmlessly WB tak pahunche, koi state change na kare.
Reorder Buffer mein "commit" kya hai? Woh in-order moment jab ek result hidden ROB se official architectural state mein move hota hai.
Speculation bit kuch faults ignore karne deta hai kyun? Galat guess wali instruction kabhi chalni hi nahi chahiye thi, isliye flush hone par uska exception discard ho jaata hai.
