Deep pipelining trade-offs: Worked examples — Hinglish deep dive

5.2.11 · D3 · Hardware › Processor Datapath & Pipelining › Deep pipelining trade-offs

Yeh page Deep pipelining trade-offs ka drill ground hai. Parent note ne ideas build kiye; yahan hum har tarah ke numbers grind karte hain jo yeh topic throw kar sakta hai — badi depths, choti depths, woh degenerate case jahan extra stages kuch nahi karte, woh limit jab depth infinity tak jaati hai, ek real chip (Pentium 4), aur ek exam twist.

Ek bhi example se pehle, ek promise: neeche har symbol parent note mein earn kiya gaya hai. Quick refresh, plain words mein:

Definition Woh quantities jinhe hum juggle karte hain

$T_{0}$ — ek instruction ki total logic delay jab koi pipelining nahi hai, nanoseconds (ns) mein measured. Puri assembly line ko ek giant worker mein collapse hua imagine karo.
$t_{reg}$ — pipeline-register overhead: woh fixed toll (setup time + clock-to-Q + skew) jo har baar pay karna padta hai jab work ek stage boundary ke paas handover hoti hai, woh bhi ns mein. Uss moment ko imagine karo jab pizza next station ko pass kiya jaata hai — chahe task kitna bhi chota ho, hamesha ek beat lagta hai.
$k$ — stages ki sankhya jisme hum line ko slice karte hain (ek plain count, koi units nahi).
$CPI$ — cycles per instruction: average mein, ek instruction complete karne mein kitne clock ticks lagte hain. Units: cycles/instruction. Perfect pipeline mein har tick ek instruction finish hoti hai, toh $CPI = 1$ ; har stall (ek wasted tick jo hazard ka intezaar mein kharch hoti hai) usse badhata hai. Isliye $CPI = 1 + (stall cycles per instruction)$ .

Frequency $1/ T_{cycle}$ kyun hai aur kuch fancier nahi: frequency literally ka matlab hai "ek second mein kitne cycles fit hote hain", aur agar ek cycle $T_{cycle}$ seconds chalti hai, toh $1/ T_{cycle}$ cycles ek second mein fit hoti hain. Agar $T_{cycle}$ nanoseconds ( $1 0^{- 9}$ s) mein hai, toh $f = 1000/ T_{cycle}$ megahertz (MHz) deta hai, kyunki $1 ns = 1 0^{- 9} s$ aur $1 MHz = 1 0^{6}$ ticks/s.

The scenario matrix

Yeh topic jo bhi problem pose kar sakta hai woh in cells mein se kisi ek mein fall karta hai. Neeche ke worked examples mein cell(s) ka label hai jise woh cover karte hain, toh sab milke koi gap nahi chorte.

Cell	Kya isko distinct banata hai	Covered by
A. Shallow depth	Chota $k$ (e.g. 5) — registers cycle ka ek chota hissa hain	Ex 1
B. Deep depth	Bada $k$ (e.g. 20) — registers bada hissa khaate hain; diminishing returns visible	Ex 2
C. Ratio comparison	" $k_{2}$ , $k_{1}$ se kitna better hai?" — woh marginal sawaal	Ex 3
D. Limiting case	$k \to \infty$ — speedup ki hard ceiling	Ex 4
E. Degenerate input	$t_{reg} = 0$ , ya $k = 1$ (bilkul pipeline nahi) — sanity anchors	Ex 5
F. Hazards fold in	Branches CPI badhate hain; frequency win partly kha jaati hai	Ex 6
G. Imbalanced stages	"Sirf evenly divide karo" wala trap — longest stage rules	Ex 7
H. Real-world word problem	Pentium 4: frequency upar gaya par net performance flat raha	Ex 8
I. Power / DVFS twist	Dynamic power scaling — exam-style curveball	Ex 9

Hum ek baseline machine reuse karte hain jab tak koi cell aur na kahe: $T_{0} = 10 ns, t_{reg} = 0.2 ns .$

Example 1 — Shallow depth (Cell A)

Forecast: Pehle guess karo — kya speedup $5 \times$ ke karib hoga, ya clearly kam? Ek number likho.

Stage logic delay $τ = T_{0} / k = 10/5 = 2 ns$ . Yeh step kyun? Even splitting ka matlab hai har stage ko kaam ka equal $1/ k$ share milta hai; $τ$ woh share hai aur yahi cycle ka useful part set karta hai.
Cycle time $T_{cycle} = τ + t_{reg} = 2 + 0.2 = 2.2 ns$ . Yeh step kyun? Ek cycle slowest stage plus next stage mein cross karne ke toll se choti nahi ho sakti — register overhead hamesha pay karna padta hai.
Frequency $f = 1000/ T_{cycle} = 1000/2.2 \approx 454.5 MHz$ . Yeh step kyun? "Ek tick 2.2 ns leti hai" ko "kitne ticks per second" mein convert karte hain; woh $1000$ ns ko MHz mein badalta hai.
Speedup $= T_{0} / T_{cycle} = 10/2.2 \approx 4.55 \times$ . Yeh step kyun? Unpipelined machine har instruction $10$ ns mein finish karta hai; pipeline har instruction $2.2$ ns mein finish karta hai jab pipe full ho jaati hai.

Verify: Cycle mein register overhead fraction $0.2/2.2 \approx 9%$ hai — chota, jaise shallow pipelines ke liye promise kiya tha. Aur $4.55 < 5$ , toh hume ideal $5 \times$ nahi mila: $0.2$ ns toll ne woh missing $0.45 \times$ kha liya. Sanity: $4.55 \times 2.2 = 10.0$ ns ✓.

Example 2 — Deep depth (Cell B)

Forecast: Humne Ex 1 se depth chaar guna badhayi (5→20). Kya speedup bhi $\approx 18 \times$ tak chaar guna ho jaayega? Guess karo.

$τ = 10/20 = 0.5 ns$ . Kyun? Ab har stage woh kaam karta hai jo $k = 5$ par ek-chauthaayi karta tha.
$T_{cycle} = 0.5 + 0.2 = 0.7 ns$ . Kyun? Same toll ( $0.2$ ), lekin ab yeh ek choti cycle ka bada hissa hai.
$f = 1000/0.7 \approx 1428.6 MHz$ . Kyun? Ticks/s mein convert karo.
$Speedup = 10/0.7 \approx 14.29 \times$ . Kyun? Unpipelined ke mukable throughput ratio.

Verify: Ab overhead fraction $0.2/0.7 \approx 29%$ hai — Ex 1 ke $9%$ se tigunaH zyada. Yahi exactly wajah hai ki 5→20 stages jaana (ek $4 \times$ deepening) sirf $14.29/4.55 \approx 3.14 \times$ zyada speedup laya, $4 \times$ nahi. Register toll har cycle ka zyada hissa chura raha hai. ✓

Example 3 — Marginal comparison (Cell C)

Forecast: Stages double kiye — kya frequency double ho jaayegi?

$τ = 10/10 = 1 ns$ , toh $T_{cycle} = 1 + 0.2 = 1.2 ns$ . Kyun? Same recipe.
$f_{10} = 1000/1.2 \approx 833.3 MHz$ . Kyun? Ticks/s.
$S_{10} = 10/1.2 \approx 8.33 \times$ . Kyun? Unpipelined ke mukable speedup.
Ex 1 se ratio: $S_{10} / S_{5} = 8.33/4.55 \approx 1.83 \times$ . Yeh step kyun? Yeh depth double karne ka asli payoff hai — woh number jo ek designer actually care karta hai.

Verify: Humne $k$ double kiya lekin sirf $1.83 \times$ mila, $2 \times$ nahi. Woh missing $0.17 \times$ register toll hai jo apne aap ko assert kar raha hai — aur neeche Figure 1 dikhata hai ki yeh point curve par exactly kahan baithta hai. ✓

Figure 1 padhna (upar ke numbers se jodo): dashed yellow line ideal speedup $= k$ hai (jo tum paate agar $t_{reg} = 0$ hota, humara Ex 5a result). Solid blue curve hamare formula se real speedup hai. Teen white dots dhundho: $k = 5$ par $4.5 \times$ (Ex 1) padhta hai, $k = 10$ par $8.3 \times$ (yeh example), $k = 20$ par $14.3 \times$ (Ex 2). Blue aur yellow ke beech vertical gap dekho jo daayein jaate waqt badh rahi hai — woh badhta gap register toll hai, aur yahi wajah hai ki marginal ratio ideal $2 \times$ se girikar hamare $1.83 \times$ ho gayi. Pink dotted line $50$ par Ex 4 ki woh ceiling hai jiske taraf blue curve creep karta hai lekin kabhi touch nahi karta.

Example 4 — The limit (Cell D)

Forecast: Kya speedup hamesha badhta rehta hai, ya ek wall se takraata hai? Woh number kya hai?

$Speedup (k) = \frac{T _{0}}{\frac{T _{0}}{k} + t _{reg}}$ se shuru karo. Kyun? Yeh hamaara exact formula hai — abhi koi approximation nahi.
Jab $k \to \infty$ , term $\frac{T _{0}}{k} \to 0$ . Yeh step kyun? Ek fixed $T_{0} = 10$ ko bade $k$ se divide karne par woh zero ki taraf shrink hota hai — har stage ka useful kaam gayab ho jaata hai.
Toh $Speedup \to \frac{T _{0}}{t _{reg}} = \frac{10}{0.2} = 50 \times$ . Kyun? Logic term gayab hone ke baad, sirf toll denominator mein bachta hai, aur woh ek fixed $0.2$ hai.

Verify: Chahe tum kitne bhi stages banao, is machine par tum $50 \times$ kabhi beat nahi kar sakte. Bade $k$ se check karo: $k = 1000$ par, $T_{cycle} = 0.01 + 0.2 = 0.21$ , speedup $= 10/0.21 \approx 47.6 \times$ — 50 ki taraf creep kar raha hai lekin kabhi pahunch nahi raha. Figure 1 par yeh pink dotted asymptote hai. Yeh register-limited regime hai jiske baare mein parent note ne warning di thi. ✓

Example 5 — Degenerate inputs (Cell E)

Forecast: (a) mein speedup exactly kya hona chahiye? (b) mein koi speedup hona chahiye?

Case (a): $t_{reg} = 0$

$T_{cycle} = T_{0} / k + 0 = 10/20 = 0.5 ns$ . Kyun? Toll bilkul hata do.
$Speedup = 10/0.5 = 20 \times$ . Yeh step kyun? Zero overhead ke saath, speedup exactly $k$ ke barabar hai — woh ideal jo Figure 1 mein dashed yellow line represent karti hai.

Case (b): $k = 1$

$T_{cycle} = 10/1 + 0.2 = 10.2 ns$ . Kyun? Ek "stage" sabhi logic hold karta hai, phir bhi result latch karne ke liye hum ek register toll pay karte hain.
$Speedup = 10/10.2 \approx 0.98 \times$ . Yeh step kyun? Register add karna lekin splitting nahi karna tumhe unpipelined se thoda slow bana deta hai — ek pure loss.

Verify: (a) confirm karta hai $t_{reg} = 0 \Rightarrow speedup = k$ , theoretical best. (b) confirm karta hai $k = 1$ kabhi worth it nahi (0.98 < 1) — pipelining tabhi pay karti hai jab $k \geq 2$ aur frequency gain ek-time toll ko outweigh kare. Dono anchors theek behave kar rahe hain. ✓

Example 6 — Hazards fold in (Cell F)

Forecast: Frequency 20 stages par $\sim 3 \times$ zyada hai. Kya effective speedup bhi $\sim 3 \times$ hoga? Ya kam?

Mispredictions per instruction $= 0.1 \times \frac{1}{5} = 0.02$ . Kyun? $\frac{1}{5}$ instructions branches hain; unme se $10%$ mispredicted hain.
CPI (5-stage) $= 1 + 0.02 \times (5 - 1) = 1 + 0.08 = 1.08$ . Yeh step kyun? Har misprediction $k - 1 = 4$ stages flush karta hai; multiply karo kitni baar hota hai aur base CPI 1 mein add karo.
CPI (20-stage) $= 1 + 0.02 \times (20 - 1) = 1 + 0.38 = 1.38$ . Kyun? Ab $k - 1 = 19$ instructions har misprediction par flush hote hain — lagbhag $5 \times$ zyada dard.
Effective speedup ratio $\frac{f _{20}}{f _{5}} \times \frac{CPI _{5}}{CPI _{20}} = \frac{1428.6}{454.5} \times \frac{1.08}{1.38}$ . Yeh step kyun? Performance $= f / CPI$ ; performances ka ratio = (frequency ratio) × (inverse CPI ratio).
Compute: $3.143 \times 0.7826 \approx 2.46 \times$ . Kyun? $3.14 \times$ ka raw frequency gain khinchkar $2.46 \times$ ho jaata hai kharab CPI ki wajah se.

Verify: Frequency akele ne $3.14 \times$ kaha; hazards ne isse ghaatakar $2.46 \times$ kar diya. CPI penalty ( $1.38/1.08 = 1.28$ ) ne frequency win ka lagbhag $22%$ kha liya. Isliye Branch Prediction accuracy deep pipelines mein life or death hai — dekhein bhi Pipeline Hazards. ✓

Example 7 — Imbalanced stages (Cell G)

Forecast: Average stage $1.0$ ns hai. Kya clock average par run karta hai?

Sabse lamba stage dhundho. List mein maximum $1.5 ns$ hai. Yeh step kyun? Har stage clock tick se pehle finish hona chahiye; clock slowest worker ka intezaar karta hai, kabhi average ka nahi.
$T_{cycle} = 1.5 + 0.2 = 1.7 ns$ . Kyun? Longest stage plus fixed register toll.
$Speedup = 10/1.7 \approx 5.88 \times$ . Kyun? Unpipelined ke mukable throughput.
Balanced Ex 3 se compare karo ( $8.33 \times$ ). Yeh step kyun? Dikhata hai imbalance kitna costing karta hai.

Verify: Naive even-split ne $8.33 \times$ predict kiya tha; real imbalanced pipeline sirf $5.88 \times$ deliver karta hai — lagbhag $29%$ ka loss, poori tarah uss ek $1.5$ ns stage ki wajah se. Delays ka sum ab bhi $\sum = 10.0$ ns hai (average $1.0$ ), phir bhi max hi rule karta hai. Kabhi average mat lo — hamesha max lo. ✓

Figure 2 padhna (upar ke numbers se jodo): har blue bar ek stage ki logic delay hai; $x$ -axis stage number hai, $y$ -axis delay ns mein hai. Woh akela pink bar stage 4 hai $1.5$ ns par — sabse lamba. $1.5$ par khinchi pink dashed line woh hai jo actually $T_{cycle}$ set karti hai ( $t_{reg}$ add karo toh $1.7$ milta hai). Yellow dotted line $1.0$ par average mark karti hai — notice karo yeh pink line ke neeche baithti hai, aur yahi poori baat hai: clock sabse lamba bar maanta hai, toh har chota stage (pink line ke neeche wale sabhi) bacha hua waqt idle rehte hain, use waste karte hain. Woh wasted gap hi wajah hai ki speedup $8.33 \times$ se girikar $5.88 \times$ ho gaya.

Example 8 — Real-world word problem: Pentium 4 (Cell H)

Forecast: $50%$ zyada frequency — surely faster hoga?

Performance = $f / CPI$ . Northwood ke liye: $Perf_{N} = f /1.0 = f$ . Kyun? Throughput ticks/s divided by cycles/instruction hai.
Prescott: $Perf_{P} = 1.5 f /1.5 = f$ . Yeh step kyun? Dono factors exactly $1.5 \times$ se move kiye — ek help karta, ek hurt karta.
Ratio $Perf_{P} / Perf_{N} = f / f = 1.0 \times$ . Kyun? Gains precisely cancel ho gaye.

Verify: Frequency $1.5 \times$ badhi lekin performance $1.0 \times$ badhi — zero net gain, bilkul wahi jo parent note ne "deep-pipeline wall" kaha tha. Saath hi dynamic power (Ex 9) badh gayi, toh Prescott per watt worse tha. Intel ka jawab: deep pipes ko chhhod ke 14-stage Core design apnaya jisme wider issue (Superscalar Architectures) aur better IPC tha. ✓

Example 9 — Power / DVFS twist (Cell I)

Forecast: Frequency $\sim 1.7 \times$ badhi — kya power ki poori kahani bas yahi hai?

Frequency ratio $\frac{f _{20}}{f _{10}} = \frac{1428.6}{833.3} \approx 1.714$ . Kyun? Examples 2 aur 3 se.
Power ratio $\frac{P _{20}}{P _{10}} = \frac{C _{20}}{C _{10}} \cdot \frac{V ^{2}}{V ^{2}} \cdot \frac{f _{20}}{f _{10}} = 1.1 \times 1 \times 1.714$ . Yeh step kyun? $V$ cancel ho jaata hai (constant rakha); capacitance aur frequency dono multiply hote hain.
Evaluate: $1.1 \times 1.714 \approx 1.886$ . Toh dynamic power $\approx 1.89 \times$ factor se badhti hai. Yeh step kyun? Hum actually numbers multiply karte hain final answer paane ke liye — symbolic nahi chodna.

Verify: Power $\approx 1.89 \times$ badhi jabki performance (roughly frequency, $1.71 \times$ ) kam badhi — toh power performance se zyada tezi se badhi ( $1.89 > 1.71$ ), matlab worse efficiency (zyada watts per instruction). Yahi exactly wajah hai ki real chips $V$ neeche laate hain jab stages add karte hain, DVFS use karke; kyunki $P \propto V^{2}$ , thoda voltage drop bahut power recover karta hai. Aur $2 \times$ registers mein clock distribution khud ek major power sink hai (Pentium 4 mein 30–40%). ✓

Recall Self-test — answers cover karo

Even 5→20 stages kya speedup ratio deta hai (register-limited)? ::: Lagbhag $3.14 \times$ , $4 \times$ nahi (Ex 2 ÷ Ex 1). Baseline machine par absolute speedup ceiling kya hai? ::: $T_{0} / t_{reg} = 10/0.2 = 50 \times$ (Ex 4). Real register ke saath $k = 1$ par speedup kya hai? ::: $\approx 0.98 \times$ — unpipelined se thoda worse (Ex 5b). Imbalanced pipeline mein cycle time kya set karta hai? ::: Sabse lamba stage plus $t_{reg}$ , kabhi average nahi (Ex 7). Prescott ka $1.5 \times$ frequency $1.0 \times$ performance kyun deta hai? ::: CPI bhi $1.5 \times$ badhi, gain cancel ho gaya (Ex 8). Ex 9 mein dynamic power kis factor se badhi? ::: $\approx 1.89 \times$ , $1.71 \times$ frequency gain se zyada — worse efficiency.

Connections: Instruction Pipelining Basics · Pipeline Hazards · Branch Prediction · Superscalar Architectures · Clock Distribution and Skew · Dynamic Voltage and Frequency Scaling (DVFS) · Pentium 4 vs Core Microarchitecture · 5.2.11 Deep pipelining trade-offs (Hinglish)