Deep pipelining trade-offs: Question bank — Hinglish deep dive

5.2.11 · D5 · Hardware › Processor Datapath & Pipelining › Deep pipelining trade-offs

Yeh ek concept-trap question bank hai parent topic ke liye. Neeche har item ek one-line reveal hai: prompt padho, apne dimaag mein jawab sochho, phir dekhlo. Goal arithmetic nahi hai (woh worked-example pages mein hai) — balki woh galat intuitions pakadna hai jo deep pipelining chup-chaap invite karta hai.

Shuru karne se pehle, woh kuch symbols jinhe hum baar baar use karte hain, simple language mein:

Stage — assembly line par ek work-station; ek instruction ek clock tick mein ek stage mein rehta hai.
$T_{0}$ (un-pipelined total logic delay) — woh time jitna lagta hai instruction ka saara combinational kaam ek lambe block mein karne mein, stages mein kaatne se pehle. Isse poori pizza-making ka time samjho end to end, bina kisi hand-off ke.
$k$ — stages ki sankhya jisme hum $T_{0}$ ko kaatthe hain.
$τ$ (per-stage logic delay) — ek stage mein bacha combinational kaam. Agar hum $T_{0}$ ko evenly split karein, toh $τ = T_{0} / k$ ; jab emphasise karna ho ki yeh sirf logic hai, register cost nahi, tab hum $τ_{logic}$ bhi likhte hain.
$t_{reg}$ (register overhead) — stages ke beech kaam handover karne ka fixed per-stage tax: $t_{reg} = t_{setup} + t_{clk-to-Q} + t_{skew} + t_{jitter}$ .
Cycle time ( $T_{cycle}$ ) — ek tick kitni der chalti hai, jo slowest stage ki logic plus us overhead se set hoti hai: $T_{cycle} = τ + t_{reg}$ .
$f$ (clock frequency) — ek second mein kitni ticks hoti hain; yeh sirf cycle time ka ulta hai, $f = 1/ T_{cycle}$ . Chhota cycle matlab bada $f$ .
CPI — cycles per instruction; kitni ticks, average mein, har instruction actually cost karti hai jab stalls aur flushes count ho jaate hain.
IPC (instructions per cycle) — CPI ka doosra pehlu, $IPC = 1/ CPI$ ; kitna useful kaam har tick mein complete hota hai. Deep pipelines $f$ badhate hain lekin IPC girate hain.
Throughput — real delivered performance, $f / CPI$ ke barabar (ya $f \cdot IPC$ ). $f$ aur CPI dono matter karte hain, yehi is page ka poora moral hai.
$C$ (load capacitance) aur $V$ (supply voltage) — dynamic-power law $P \propto C V^{2} f$ mein, $C$ woh electrical charge hai jo circuit ko har switch par swing karna padta hai (zyada registers matlab zyada $C$ ) aur $V$ woh voltage hai jis par woh swing karta hai.

Figure 1 (neeche) woh speedup curve plot karta hai. Apni ungli se trace karo: magenta line chhote $k$ par tezi se chadhti hai, phir modti hai aur violet dashed ceiling $T_{0} / t_{reg}$ ko hug karti hai, jabki orange dotted "ideal" line (woh fantasy jahan $t_{reg} = 0$ ) hamesha chadhti rehti hai. Magenta aur orange ke beech ka gap hi register tax hai. Is page par har "diminishing returns" wala jawab actually usi bend ko point kar raha hai.

Figure 2 (neeche) story ka doosra aadha dikhata hai. Har bar woh instructions ki sankhya hai jo ek galat branch guess throw away karta hai — height $k - 1$ . Dekho yeh seedhi line ki tarah badhta hai: 5 stages par 4 flush, 31 par 30. Frequency (Figure 1) deta hai, hazards (Figure 2) waapis lete hain — aur lena depth ke saath tezi se badhta jaata hai.

True or false — justify

A 20-stage pipeline runs 4× faster than a 5-stage one at the same logic

False — frequency tabhi badhti hai jab slowest stage 4× shrink kare, aur register overhead

t_{reg}

ek fixed tax hai jo stages ke patla hone par zyada share khaata hai, toh speedup 4× se kaafi kam rehta hai (yahi Figure 1 mein bend hai).

Making each stage do less work always shortens the clock period

False — yeh logic wala part

τ

toh shortens karta hai, lekin

t_{setup} + t_{clk-to-Q} + t_{skew}

wahin rehta hai, toh jab

τ

tiny ho jaata hai toh period shrink karna band ho jaata hai (register-limited regime — Figure 1 ka flat part).

The purely analytical model says "deeper is always better"

True — cycle-time function

T_{cycle} (k) = T_{0} / k + t_{reg}

k

ke respect mein differentiate karne par

\frac{d T _{cycle}}{d k} = - T_{0} / k^{2}

milta hai, jo hamesha negative hai, toh period girta rehta hai; model isliye galat hai kyunki woh hazards aur power ignore karta hai, math galat hai isliye nahi.

Branch misprediction penalty is a fixed 4 cycles regardless of depth

False — penalty roughly

k - 1

cycles hoti hai kyunki tum branch ke peeche fetch ki gayi har instruction flush karte ho; ek 20-stage pipeline ~19 throw away karta hai, ek 31-stage wala ~30 (yahi Figure 2 ki seedhi climb hai).

Doubling frequency doubles throughput, all else equal

True as a principle — throughput

f / CPI

hai, toh agar CPI fixed rakha jaaye,

f

double karne se woh double hoti hai; trap yeh hai ki deep pipelining shayad hi CPI ko fixed rakhti hai (zyada stalls aur flushes CPI upar push karte hain), toh practice mein doubling partly cancel ho jaati hai.

Adding pipeline registers costs power even when the pipeline is idle

True — clock network ko phir bhi saare

k

register banks ko har tick toggle karna padta hai, isliye Pentium 4 apna 30–40% power sirf clock distribute karne mein lagata tha.

Perfect stage balance is achievable if you just divide the logic evenly

False — kuch operations atomic hote hain (ek cache access, ek TLB lookup) jo beech mein nahi kaate ja sakte, toh real stage delays uneven hote hain aur sabse lamba wala clock set karta hai.

Higher clock frequency alone made Pentium 4 Prescott faster than Northwood

False — frequency ~1.5× badhi lekin CPI bhi ~1.5× worsened longer misprediction penalty se, toh per-clock performance

f / CPI

~1.0× par aa gayi — essentially flat.

With perfect branch prediction, deep pipelining has no downside

False — 100% prediction par bhi tum register overhead, stage-imbalance waste, aur quadratically-scaling clock/register power pay karte ho.

The register overhead

t_{reg}

includes clock skew

True —

t_{reg} = t_{setup} + t_{clk-to-Q} + t_{skew} + t_{jitter}

; skew registers ke across clock edge ki arrival-time mismatch hai, ek real fixed cost jo har stage ko budget karni padti hai.

Spot the error

"10 ns logic split into 10 stages gives exactly 1 ns cycle time."

Error —

T_{0} = 10

ns aur

k = 10

ke saath logic per stage

τ = T_{0} / k = 1

ns hai, lekin cycle

τ + t_{reg} = 1 + t_{reg}

hai; saath hi real logic das equal 1 ns pieces mein split nahi hogi, toh sabse lamba stage govern karta hai.

"Deeper pipelines are always slower because hazards dominate."

Error — deeper pipelines aksar frequency badhate hain; net slower hain ya nahi yeh is par depend karta hai ki CPI penalty frequency gain se zyada hai ya kam, jo ek trade-off hai, guarantee nahi.

"Speedup from a

k

-stage pipeline approaches

k

k \to \infty

Error — even splitting

τ = T_{0} / k

ke saath,

Speedup = \frac{T _{0}}{T _{0} / k + t _{reg}}

ek fixed ceiling

T_{0} / t_{reg}

approach karta hai jo register delay se set hoti hai,

k

se nahi (Figure 1 mein magenta orange se bend ho kar door jaati hai).

"A data hazard in a 31-stage pipeline is the same 1–2 cycle stall as in a 5-stage one."

Error — ek operand kai zyada stages downstream tak ready nahi ho sakta, toh bypassing zyada complex ho jaata hai aur residual stalls badhte hain; 1–2 cycle figure ek 5-stage artifact hai.

"Reducing voltage cancels the extra power of a deeper pipeline entirely."

Error — dynamic-power law

P \propto C V^{2} f

mein (jahan

C

= load capacitance,

V

= supply voltage),

V

kam karna help karta hai, lekin added registers

C

badhate hain aur higher $f$

f

badhata hai, toh yeh sirf partly offset karta hai genuinely larger power draw ko —

V

f

ke against trade karne ki technique DVFS hai, Dynamic Voltage and Frequency Scaling, jo Dynamic Voltage and Frequency Scaling (DVFS) mein cover ki gayi hai.

"CPI of 1 means the pipeline is optimal."

Error — CPI cycles per instruction count karta hai lekin yeh ignore karta hai ki har cycle kitni lambi hai; ek slow, low-CPI design ek fast, higher-CPI wale se haar sakta hai kyunki performance

f / CPI

hai.

"Forwarding paths grow linearly with pipeline depth."

Error — potential source-to-destination bypasses ki sankhya

O (k^{2})

ki tarah scale hoti hai, jo ek bada reason hai ki deep pipelines verify karna mushkil hota hai.

Why questions

Why does register overhead cap the speedup instead of hazards, in the idealized model?

Kyunki ideal model assume karta hai ki koi hazards nahi aur perfect balance hai, isliye sirf surviving fixed cost

t_{reg}

hai — toh jab

k

badhta hai logic term

T_{0} / k

vanish ho jaata hai aur curve Figure 1 mein violet ceiling

T_{0} / t_{reg}

par flatten ho jaati hai; hazards sirf realistic model mein enter karte hain.

Why did Intel abandon the deep-pipeline path for the Core architecture?

Kyunki Prescott ne "deep-pipeline wall" hit ki jo tum dono figures ko ek saath padh kar dekh sakte ho — Figure 1 ke frequency gains flat ho gaye the jabki Figure 2 ka flush penalty ~30 tak balloon ho gaya, toh falling IPC plus ~115 W power ne near-zero net gain diya; Core shallower (~14 stages) lekin wider gayi IPC badhane ke liye — dekho Pentium 4 vs Core Microarchitecture.

Why does a deeper pipeline make Branch Prediction more important, not less?

Kyunki misprediction penalty Figure 2 mein bar ki height (

k - 1

) hai, har galat guess depth badhne par bahut zyada cost karta hai, toh same accuracy chup-chaap zyada throughput lose karne lagti hai — better prediction sirf aage khade rehne ke liye chahiye hoti hai.

Why do memory stages resist being sliced thinner?

Kyunki ek cache ya TLB access atomic aur variable-latency hoti hai (hit aur miss mein bahut alag time lagta hai); tum access ke beech mein pause nahi kar sakte, toh woh stage ek hard floor banata hai ki stage kitni short ho sakti hai, Figure 1 par tum kitna right travel kar sakte ho yeh cap karta hai.

Why is "more stages = higher IPC" the wrong expectation?

Kyunki extra stages frequency badhate hain (

f

, Figure 1), IPC nahi; IPC aksar depth ke saath girta hai jab growing flush penalty (Figure 2) aur extra stalls CPI ko upar push karte hain — exactly wahi jo Prescott ka IPC ~1.5 se ~1.0 tak le gaya.

Why does the clock network dominate power in very deep pipelines?

Kyunki

k

f

par har cycle clock kiya jaata hai, toh

P \propto C V^{2} f

mein capacitance

C

(zyada registers) aur

f

dono saath badhte hain — dekho Clock Distribution and Skew.

Why can a superscalar design beat a deeper scalar one at the same frequency?

Kyunki ek cycle mein kai instructions issue karna CPI ko directly attack karta hai (IPC badhata hai, har tick mein zyada useful kaam), jabki pipe ko deep karna

f

attack karta hai jabki CPI kharaab karta hai — often

f / CPI

balance mein ek better trade.

Edge cases

What happens to speedup when

t_{reg} = 0

Tab

T_{cycle} = τ = T_{0} / k

aur

Speedup = k

exactly — yahi Figure 1 mein orange dotted "ideal" line hai jo kabhi nahi modti — isliye

t_{reg}

woh single term hai jo real (magenta) curve ko uski ceiling ki taraf kheenchta hai.

What is the pipeline period when logic delay

τ_{logic} \to 0

Yeh

T_{cycle} \approx t_{reg}

par flatten ho jaata hai — register-limited regime, Figure 1 ka flat right end — toh zyada stages add karne se essentially kuch nahi milta.

For a 2-stage pipeline (

k = 2

) versus un-pipelined, does the formula still show a gain?

Haan —

Speedup (2) = \frac{2 T _{0}}{T _{0} + 2 t _{reg}}

, jo 1 se upar hai jab bhi

t_{reg} < T_{0} /2

; lekin note karo ki ek "1-stage pipeline" (

k = 1

) sirf un-pipelined logic plus ek register hai, toh woh thoda slow hai — pipelining tabhi pay karti hai jab

k \geq 2

If branch prediction were perfect (100%), does the control-hazard penalty vanish for any

k

Haan, misprediction term (Figure 2 ke bars) depth se regardless zero ho jaati hai — lekin data hazards, stage imbalance, aur register/power costs rehte hain, toh depth ki phir bhi limits hain.

Where does the empirical sweet spot

k^{*} \approx 10

–15 come from?

Yeh wahan hai jahan dono figures importance mein cross karte hain:

k \approx 10

–15 tak Figure 1 ka frequency curve apna zyaadatar 2–3× gain capture kar chuka hota hai (register overhead cycle ka tolerable ~10–20% hai), jabki Figure 2 ka flush penalty abhi itna chhota hai ki ek 95%+ predictor CPI ko check mein rakh sakta hai — isse aage jaao toh hazard/power costs, flattening frequency benefit se tez badhte hain, toh measured throughput

f / CPI

turn over kar leta hai. Yeh real designs ka ek empirical balance hai, clean closed-form root nahi.

What throughput trend appears as

k

grows past that sweet spot?

Frequency gains flatten ho jaate hain (Figure 1 ki ceiling) jabki hazard penalties badhti rehti hain (Figure 2 ki seedhi line), toh throughput

f / CPI

peak karta hai aur phir decrease hota hai — diminishing-then-negative returns region.

Recall Fastest gut-check

Real performance ==throughput $= f / CPI$ == hai (jahan $f = 1/ T_{cycle}$ clock frequency hai), sirf $f$ nahi — deep pipelining hamesha numerator badhata hai lekin aksar denominator bhi badhata hai, aur register overhead cap karta hai ki numerator kitna ja sakta hai via $Speedup \to T_{0} / t_{reg}$ .