Deep pipelining trade-offs — Hinglish notes

5.2.11 · Hardware › Processor Datapath & Pipelining

Deep Pipelining Kya Hai?

Deep kyun jaate hain?
Frequency $f = \frac{1}{T _{cycle}}$ jahan $T_{cycle}$ sabse slow pipeline stage se determine hoti hai. Ek lambi stage ko do chhoti stages mein split karne se $T_{cycle}$ reduce ho sakta hai, $f$ boost hoti hai.

Kaam kaise karta hai?

Logic blocks ke beech additional pipeline registers insert karo
Har stage kam combinational work karti hai → shorter critical path
Clock tezi se tick kar sakta hai kyunki har stage pehle complete ho jaati hai

Ideal Speedup Model (Aur Yeh Kyun Toot Ta Hai)

Derivation:

Unpipelined: total delay = $k \cdot τ$ (sab logic ek cycle mein)
Pipelined: cycle time = $τ + t_{reg}$ (slowest stage + register overhead)
Speedup = $\frac{k \cdot τ}{τ + t _{reg}}$
Jab $k \to \infty$ : agar $τ = \frac{T _{0}}{k}$ (evenly split karo), speedup $\to \frac{T _{0}}{t _{reg}}$ — register delay se bounded

Yeh kyun important hai: Register overhead bottleneck ban jaata hai. Agar $t_{reg} = 0.1 τ$ hai, toh stages 10 se 20 double karne par sirf ~10% speedup milta hai, 2× nahi.

Real Trade-offs

1. Pipeline Register Overhead

Yeh gains kyun khatam kar deta hai?

5 stages par: $τ_{logic}$ shayad $t_{reg}$ se 10× bada ho → registers ~10% overhead hain
31 stages par (Pentium 4): $τ_{logic}$ bahut chhota hai, $t_{reg}$ dominate karta hai → zyada stages add karne se barely kuch fayda

Optimal depth estimate kaise karein:
$\frac{d T _{cycle}}{d k} = 0$ set karo. Agar total logic $T_{0}$ ko $k$ stages mein split karein: $T_{cycle} (k) = \frac{T _{0}}{k} + t_{reg}$ $\frac{d}{d k} (\frac{T _{0}}{k} + t_{reg}) = - \frac{T _{0}}{k ^{2}} < 0 always$ Toh analytically, "deeper is always better" — lekin yeh hazard costs aur power ko ignore karta hai.

2. Pipeline Hazards Non-linearly Scale Karte Hain

Data hazards:

Classic 5-stage: RAW stall = forwarding ke saath 1-2 cycles
31-stage: operand 5-10 stages tak ready nahi ho sakta → complex bypassing ya zyada stalls

Control hazards:

Branch misprediction penalty = $k - 1$ cycles (baad wale sab instructions flush)
5-stage: 4 cycles waste
20-stage: 19 cycles waste — 5× worse

Real impact:
$CPI_{effective} = 1 + stall_{data} + stall_{control}$ Chahe $f$ double ho, agar stalls triple hote hain, throughput drop ho jaata hai.

3. Power aur Complexity

Clock power:
Clock network ko $k$ sets of pipeline registers drive karne padte hain. Pentium 4 ke deeply pipelined design mein clock distribution mein 30-40% power lagti thi.

Complexity:

Forwarding paths: deep pipelines mein $O (k^{2})$ potential bypasses
Control logic: 20+ stages mein dependencies track karna
Verification: sab hazard cases validate karna exponentially harder

4. Stage Imbalance

Common mistake Common Misconception: "Bas evenly divide kar do"

Galat intuition: "Agar main apna 10ns logic 10 stages mein split karun, toh har stage 1ns ki hogi."

Kyun sahi lagta hai: Math kehta hai $10/10 = 1$ .

Steel-man: Yeh assume karta hai perfectly divisible logic. Reality mein:

Kuch operations atomic hote hain (cache lookup, TLB hit — mid-access split nahi ho sakte)
Control logic mein dependencies hoti hain (decode tab tak start nahi ho sakta jab tak fetch complete na ho)
Memory stages ki variable latency hoti hai (cache miss vs. hit)

Fix:
Actual stage delays aise dikhte hain: $[0.8, 1.2, 0.9, 1.5, ...]$ ns. Sabse lamba stage (1.5 ns) $T_{cycle}$ set karta hai, chhote stages ki potential waste ho jaati hai. Deep pipelines imbalance amplify karte hain kyunki har operation thinner slice hoti hai, balance karna aur mushkil ho jaata hai.

Optimal Pipeline Depth: Sweet Spot

10-15 kyun?

Itni depth se unpipelined se 2-3× frequency boost milti hai
Hazard penalties achhi prediction (95%+ branch accuracy) ke saath manageable rehti hain
Register overhead ~10-20% cycle time (tolerable)
Common instruction mixes ke liye stage balance achievable

Modern approach:

Shallow, wide pipelines (10-14 stages, 4-8 issue width)
Raw frequency ki jagah branch prediction, out-of-order execution, large caches mein invest karo
Instruction per watt better hota hai

Deep Pipelining Kab Kaam Karta Hai

Embedded/DSP processors:

Predictable workloads (few branches)
Streaming data (no data hazards)
Fixed-function → stages perfectly balance ho sakte hain
Example: 40+ stage video codecs

Graphics pipelines:

Pixel shaders independent data process karte hain
No control hazards (SIMD execution)
Depth latency ko throughput ke liye trade karta hai (frame buffers ke liye theek hai)

Inke liye nahi:

General-purpose CPUs (unpredictable branches, varied instruction mix)
Interactive workloads (latency-sensitive)

Recall Ek 12-saal ke bacche ko samjhao

Socho tum ek factory mein sandwiches bana rahe ho. Pehle, tum sab kuch khud karte ho: bread lo, peanut butter lagao, jelly lagao, kato, wrap karo. Ek sandwich mein 5 minute lagte hain.

Phir tum split karte ho: Person 1 bread laata hai (1 min), Person 2 PB lagaata hai (1 min), Person 3 jelly lagaata hai (1 min), Person 4 kaata hai (1 min), Person 5 wrap karta hai (1 min). Ab har minute ek complete sandwich nikalti hai! Tum 5× fast ho gaye.

Lekin agar 20 logon mein split karo? Person 1 bread ka bag kholega. Person 2 ek slice nikalega. Person 3 use counter par rakhega. Ab tumhe sandwich 20 logon ke beech pass karni padegi, aur hand-off ka time (jaise tray par rakhna aur "next!" chillana) add up ho jaata hai. Aur agar koi sandwich drop kar de (jaise CPU mein ek mistake, jise "branch misprediction" kehte hain), toh tumhe step 1 se restart karna hoga, aur ab 19 log sirf khade hain kuch nahi karte, sirf 4 ki jagah.

Deep pipelining aisa hi hai: zyada workers (stages) tumhe faster bana sakte hain, lekin ek point tak hi. Uske baad, coordination overhead aur mistakes jo cost aati hai woh gain se zyada ho jaati hai.

Connections

Instruction Pipelining Basics — foundation for why we pipeline
Pipeline Hazards — data/control/structural hazards amplified in deep pipelines
Branch Prediction — critical for deep pipelines; misprediction penalty = depth
Superscalar Architectures — modern alternative: go wide (multiple issue) instead of deep
Clock Distribution and Skew — deeper pipelines need more careful clock tree design
Dynamic Voltage and Frequency Scaling (DVFS) — deep pipelines enable higher $f$ , but power becomes limiting factor
Pentium 4 vs Core Microarchitecture — case study in "deep vs. wide" design philosophy

#flashcards/hardware

Deep pipelining mein fundamental trade-off kya hai? :: Higher clock frequency (zyada stages = shorter critical path) vs. pipeline registers ka increased overhead, worse hazard penalties, aur diminishing returns kyunki register delay cycle time dominate karne lagti hai.

Pipeline register overhead speedup ko eventually kyun limit karta hai?

Har stage fixed delay

t_{reg}

(setup + clk-to-Q + skew) add karta hai. Jaise stages badhte hain, logic delay

τ

shrink hoti hai lekin

t_{reg}

constant rehti hai. Eventually

T_{cycle} \approx t_{reg}

ho jaata hai, toh zyada stages add karne se cycle time barely reduce hoti hai — tum sirf data registers se guzaar rahe ho.

Branch misprediction penalty pipeline depth

k

ke saath kaise scale karta hai?

Penalty =

k - 1

cycles (branch ke baad pipeline mein sab instructions flush karo). 5-stage pipeline mein, misprediction 4 cycles cost karti hai. 20-stage pipeline mein, 19 cycles cost karti hai — almost 5× worse, jo frequency advantage erase kar sakta hai agar branches frequent hain aur mispredictions rare nahi hain.

Intel Pentium 4 Prescott ke 31-stage pipeline ki key failure kya thi?

~4 GHz achieve karne ke bawajood (high frequency), deep pipeline ki wajah se: (1) 30-cycle branch misprediction penalty, (2) stalls ki wajah se IPC ~1.5 se ~1.0 drop hua, (3) net performance ≈ shallower designs jaisi, (4) power consumption 115W tak spike hua. Frequency gain CPI increase se cancel ho gayi.

General-purpose CPUs ke liye empirically optimal pipeline depth kya hai?

Around 10-15 stages. Yeh balance karta hai: (1) 2-3× frequency boost ke liye enough depth, (2) good branch prediction ke saath manageable hazard penalties, (3) register overhead ~10-20% of cycle time, (4) diverse instruction mix ke liye achievable stage balance. Modern CPUs (jaise Zen, Core) 12-19 stages use karte hain.

Embedded DSP processors kabhi kabhi 40+ stage pipelines successfully kyun use karte hain?

(1) Predictable workloads jisme few/no branches hain → minimal control hazards, (2) streaming data processing → samples ke beech data dependencies nahi, (3) fixed-function logic → stages perfectly balance ho sakti hain, (4) video encoding jaise applications ke liye throughput > latency. General-purpose CPUs mein yeh properties nahi hote.