Foundations — Deep pipelining trade-offs

5.2.11 · D1 · Hardware › Processor Datapath & Pipelining › Deep pipelining trade-offs

0. Woh picture jis par sab kuch baith ta hai: the assembly line

Kisi bhi symbol se pehle, dekho ki pipeline kya hoti hai.

Har instruction (ek car body) fixed stations (stages) mein left se right move karti hai. Har clock tick par, sab ek saath ek station right shift karte hain. Red car woh hai jo hum follow kar rahe hain; uske peeche black cars pehle se kaam mein hain. Woh "sab ek saath" hi poora trick hai — jab ek instruction decode ho rahi hai, doosri fetch ho rahi hai.

Neeche sab kuch is picture ko describe karne wale numbers hain.

1. Har tick ka time: $T_{\text{cycle}}$

Picture: assembly-line figure mein, $T_{\text{cycle}}$ shifts ke beech pause ki length hai. Ise chota karo → cars zyada baar move karti hain → zyada cars per second khatam hoti hain.

Topic ko isko kyun chahiye: deep pipelining ka poora game $T_{\text{cycle}}$ ko shrink karna hai. Har trade-off ultimately yahi hai — "kya $T_{\text{cycle}}$ chota hua, aur kis cost par?"

Kyunki sab stations ek saath shift karte hain, sabko ek jitna time milta hai. Isliye $T_{\text{cycle}}$ sabse slow station se chota nahi ho sakta — chain apni slowest link jitni slow hoti hai.

2. Ticks per second: $f$ aur kyun $f=1/T_{\text{cycle}}$

Yeh exact formula kyun? Agar har tick $T_{\text{cycle}}$ seconds leti hai, toh ek poore second mein tum fit kar sakte ho $f=\frac{1}{T_{\text{cycle}}}.$ Yeh bas "ek second mein kitne 2-ns gaps fit hote hain?" hai — yeh physics nahi, counting hai. Hum reciprocal (one-over) use karte hain kyunki "time per event" aur "events per time" hamesha reciprocals hote hain, jaise "seconds per lap" aur "laps per second" hote hain.

Topic ko isko kyun chahiye: designers frequency advertise karte hain, lekin frequency sirf cycle time ke baare mein chupaaya hua statement hai. Jab parent kehta hai "more stages → higher $f$", iska literally matlab hai "thinner stages → smaller $T_{\text{cycle}}$".

3. Ek stage mein kaam: $\tau$ (the "combinational delay")

Picture: har station ke andar, signals logic gates mein ripple karte hain jaise dominos girte hain. $\tau$ woh time hai jo aakhri domino girne mein lagta hai.

Greek letter kyun? Bas tradition — engineers $\tau$ reserve karte hain "ek choti delay" ke liye. Koi hidden meaning nahi; ise "ek stage ki think-time ka letter" samjho.

Topic ko isko kyun chahiye: ek bade station ko do mein split karne ka matlab hai ki har half ka $\tau$ chota hoga. Chota $\tau$ → chota cycle → higher $f$. Yahi poori motivation hai deeper jaane ki.

4. Stations ke beech ka glue: pipeline registers aur $t_{\text{reg}}$

Yahan woh hidden cost hai jo assembly-line picture ne nahi dikhaya. Do stations ke beech ek holding shelf hai jo ek stage ka result pakad ke rakhti hai taaki agla stage use saaf tarike se padh sake.

Woh shelf instant nahi hai. Isme teen pieces se bana time lagta hai:

Topic ko isko kyun chahiye — yeh sabse crucial hai: $t_{\text{reg}}$ ek fixed cost hai jo stages add karne par shrink nahi hota. $\tau$ shrink hota hai jab tum split karte ho; $t_{\text{reg}}$ nahi hota. Isliye real cycle time hai $T_{\text{cycle}}=\tau +t_{\text{reg}},$ aur chahe kitna bhi thin slice karo, tum kabhi $t_{\text{reg}}$ se neeche nahi ja sakte. Yahi ek fact woh wall hai jiske around poora parent note ghumta hai.

5. Stations count karna: $k$ aur total kaam $T_0$

Isse pehle ki hum keh sakein ki $k$ badhne par kya hota hai, hume "poore kaam" ke liye ek naam chahiye jo stages milkar karte hain.

Picture: $T_0$ §3 wali domino chain ki poori length hai isse stations mein kaatne se pehle. Use $k$ equal pieces mein kaato aur har piece $T_0/k$ lambi hai.

Topic ko isko kyun chahiye: $T_0$ ka naam hone ke baad, hum cycle time ko depth $k$ ke function ke roop mein likh sakte hain. $T_{\text{cycle}}(k)$ padhte hain "woh cycle time jo tum $k$ stages choose karne par paaoge" — parentheses sirf matlab hai "$T_{\text{cycle}}$ depend karta hai $k$ par", jaise "$\text{price}(\text{weight})$" ka matlab hai price weight par depend karti hai.

$T_{\text{cycle}}(k)=\underset{\text{ek stage ka }\tau }{\underbrace{\frac{T_0}{k}}}+t_{\text{reg}}.$

Jaise $k$ badhta hai pehla term zero ki taraf melt karta hai aur $T_{\text{cycle}}(k)\to t_{\text{reg}}$ — register floor. Yahi limit hai kyun "deeper" help karna band kar deta hai.

6. Har tick mein kaam, aur total throughput: CPI aur $R$

Frequency akela jhooth bolta hai, kyunki har tick useful kaam nahi karta. Hume ek doosra number chahiye.

Picture: assembly line ko hiccup karte socho — kabhi kabhi ek station ko freeze karna padta hai (ek bubble, ek khaali slot) wait karte hue. Har frozen tick ek wasted cycle hai jo instructions mein spread hoti hai, CPI ko ideal $1$ se upar le jaati hai.

Ab hum woh cheez naam de sakte hain jis ki hume actually parwah hai — instructions finished per second.

Topic ko isko kyun chahiye: deep pipelines $f$ badhate hain lekin CPI bhi badhate hain (zyada hiccups). Agar dono same factor se badhein, toh $R$ unchanged rehta hai — tum kuch nahi gain karte, exactly Pentium 4 story. $R$ woh accountant hai jo hidden losses pakadta hai. Un hiccups ke causes ki apni note hai: Pipeline Hazards.

7. Deep hone par hiccups kyun bure ho jaate hain: flush penalty $P_{\text{misp}}$

Picture: galat guess ka matlab hai ki line mein branch ke peeche currently har car scrap ho jaati hai. Ek 5-station line mein 4 cars tak scrap hoti hain ($P_{\text{misp}}=4$); ek 20-station line mein 19 tak ($P_{\text{misp}}=19$). Lambi line → galat guess par bahut bada loss. Isliye CPI $k$ ke saath climb karta hai aur isliye branch prediction accuracy deep pipelines mein itni zyada matter karti hai.

8. Power symbols: $P_{\text{dynamic}}$, $C$, $V$, $f$

$P_{\text{dynamic}}=C\cdot V^2\cdot f.$

Yeh shape kyun? Har switch ek energy $\propto C{V}^2$ move karta hai (size $C$ ka bucket pressure $V$ tak fill karne ki energy $V^2$ ke saath badhti hai), aur yeh $f$ times per second hota hai — energy per event times events per second = power. $V^2$ isliye sabse strong lever hai, jo Dynamic Voltage and Frequency Scaling (DVFS) se tied hai.

Topic ko isko kyun chahiye: deep pipelines $f$ push up karte hain aur $k$ sets of registers add karte hain (zyada $C$), isliye power do fronts par climb karti hai. Yahi woh thermal wall hai jisme Pentium 4 jakar pada.

Prerequisite map

Ise top-down padho: picture timing symbols spawn karti hai; timing $f$ deti hai; depth $k$ aur total kaam $T_0$ dono timing floor aur hazard cost mein feed karte hain; $f$ aur CPI milke throughput $R$ banate hain; poori cheez power ceiling se milti hai — aur woh collision hi topic hai.

Equipment checklist

Right side cover karo aur reveal karne se pehle har ek ka jawab dene ki koshish karo.