Foundations — Hazard detection units

Before you can read the parent note, you need to earn every word it throws at you. This page builds each symbol from nothing, in the order they depend on each other. Do not skip — each block uses only things defined above it.

1. What is an "instruction"?

The picture: think of a recipe card. Each card says one step. The CPU reads card 1, does it, then card 2, and so on.

We write instructions in assembly, a human-readable shorthand. Example:

add  $4, $2, $5

Read this as: "add the contents of register $2 and register $5, store the result in register $4." The leftmost register is always the destination (where the answer goes); the others are sources (where inputs come from).

2. What is a "register"?

The picture above: 32 labelled cubby-holes. Each holds one value. Instructions read from and write to these boxes.

3. Rs, Rt, Rd — the register slots in an instruction

Every instruction that touches registers has up to three register fields. These are just labels for which slot of the instruction we mean, not the values themselves.

For add $4, $2, $5:

• Rd = 4 (result goes to $4)
• Rs = 2, Rt = 5 (inputs)

Why the topic needs these: hazard detection is entirely about comparing numbers like "is the Rd of instruction 1 equal to the Rs of instruction 2?" If those two match, instruction 2 wants a value instruction 1 hasn't finished writing. That comparison is the hazard check.

4. The pipeline: five stages of an assembly line

Doing a whole instruction at once is slow. Instead the CPU splits the work into 5 stages and, like a factory line, works on 5 instructions at once — each in a different stage.

The picture: five columns. In any one clock tick, five different instructions each sit in a different column. Follow the orange instruction diagonally — it moves one column to the right every tick.

Why the topic needs this: a hazard exists because of overlap. If instructions ran one-at-a-time (finish IF...WB before starting the next), a later instruction would always read fully-written registers. Overlap is what makes speed and hazards possible.

5. Pipeline registers: the "gates" between stages

Between each pair of stages there is a hardware latch that snapshots everything the next stage needs. They are named after the two stages they sit between.

We write ID/EX.RegisterRd to mean "the Rd field stored in the ID/EX latch right now" — i.e. the destination register of the instruction that just moved into EX. The dot . just means "the field inside".

Why the topic needs this: the hazard unit cannot look at instructions directly — it looks at these latches. Asking "is the instruction in EX going to clash with the instruction in ID?" literally means "compare ID/EX.RegisterRd with IF/ID.RegisterRs."

6. What "hazard" actually means

The picture shows the classic load-use clash: lw (load) is still fetching its value in MEM while add (in EX) already wants that value. The red gap is the moment the data does not yet exist.

7. Control signals: 1-bit orders to the hardware

The ones the parent note uses:

Why the topic needs these: the hazard unit's whole output is a few of these signals. To stall, it sets PCWrite = 0 and IF/ID_Write = 0 (freeze the front of the pipe) and zeroes the control bits going into EX (insert a bubble).

8. The logic symbols: $\wedge$, $\vee$, $==$

The formulas in the parent are plain true/false logic. Three symbols:

So the scary-looking load-use condition

reads in English as: "the instruction in EX is a load AND its destination equals either source of the instruction in ID." That is exactly the "not-ready-yet" picture from Figure 3.

9. Bubble / NOP / stall / flush — the four actions

How it all feeds the topic

Each box is something this page defined. Follow the arrows: you cannot understand the hazard unit until every upstream box makes sense.

Equipment checklist

Test yourself — cover the right side and answer before revealing.

When every line above is instant, go read the parent: 5.2.10 Hazard detection units (Hinglish). Next stops: 5.2.9-Forwarding-unit and 5.2.11-Branch-prediction.