Hazard detection units: Foundations — Hinglish deep dive

5.2.10 · D1 · Hardware › Processor Datapath & Pipelining › Hazard detection units

Parent note padhne se pehle, tumhe har woh word earn karna hoga jo woh tumhare samne phenkta hai. Yeh page har ek symbol ko kuch nahi se build karta hai, usi order mein jisme woh ek doosre par depend karte hain. Skip mat karo — har block sirf upar defined cheezein use karta hai.

1. "Instruction" kya hoti hai?

Picture: socho ek recipe card. Har card ek step kehta hai. CPU card 1 padhta hai, karta hai, phir card 2, aur aage.

Hum instructions assembly mein likhte hain, jo ek human-readable shorthand hai. Example:

add  $4, $2, $5

Ise padhte hain: "register $2 aur register $5 ka content add karo, result ko register $4 mein store karo." Sabse left wala register hamesha destination hota hai (jahan answer jaata hai); baaki sources hote hain (jahan se inputs aate hain).

2. "Register" kya hota hai?

Upar wali picture: 32 labelled cubby-holes. Har ek ek value rakhta hai. Instructions in boxes se read aur write karte hain.

3. Rs, Rt, Rd — ek instruction mein register slots

Har instruction jo registers touch karta hai usme teen register fields tak hote hain. Yeh sirf labels hain instruction ke kaunse slot ka matlab hai, values khud nahi.

add $4, $2, $5 ke liye:

Rd = 4 (result $4 mein jaata hai)
Rs = 2, Rt = 5 (inputs)

Topic ko yeh kyun chahiye: hazard detection poori tarah "kya instruction 1 ka Rd instruction 2 ke Rs ke barabar hai?" jaise numbers compare karne ke baare mein hai. Agar woh do match karte hain, toh instruction 2 woh value chahti hai jo instruction 1 ne abhi finish nahi ki. Yeh comparison hi hazard check hai.

4. Pipeline: ek assembly line ke paanch stages

Ek instruction ek saath poori karna slow hai. Isliye CPU kaam ko 5 stages mein split karta hai aur, factory line ki tarah, ek saath 5 instructions par kaam karta hai — har ek alag stage mein.

Picture: paanch columns. Kisi bhi ek clock tick mein, paanch alag instructions har ek alag column mein hain. Orange instruction ko diagonally follow karo — yeh har tick mein ek column right move karta hai.

Topic ko yeh kyun chahiye: hazard isliye exist karta hai kyunki overlap hai. Agar instructions ek-ek karke chalte (agla shuru karne se pehle IF...WB finish karo), toh baad ki instruction hamesha fully-written registers read karti. Overlap hi speed aur hazards dono possible karta hai.

5. Pipeline registers: stages ke beech "gates"

Har do stages ke beech ek hardware latch hota hai jo next stage ko zaroori har cheez snapshot karta hai. Unhe un do stages ke naam par rakha jaata hai jinke beech woh baithe hain.

Hum ID/EX.RegisterRd likhte hain matlab "abhi ID/EX latch mein store hue Rd field" — yani us instruction ka destination register jo abhi EX mein move hua hai. Dot . ka matlab sirf "andar ka field" hai.

Topic ko yeh kyun chahiye: hazard unit instructions directly nahi dekh sakti — yeh in latches ko dekhti hai. "Kya EX mein instruction ID mein instruction ke saath clash karegi?" poochna literally matlab hai "ID/EX.RegisterRd ko IF/ID.RegisterRs se compare karo."

6. "Hazard" ka actually matlab kya hai

Picture classic load-use clash dikhata hai: lw (load) abhi MEM mein apni value fetch kar raha hai jabki add (EX mein) already woh value chahta hai. Red gap woh moment hai jab data abhi exist nahi karta.

7. Control signals: hardware ko 1-bit orders

Parent note jo use karta hai:

Signal	Jab 1 hota hai matlab
`MemRead`	yeh instruction data memory read karti hai (yeh load hai)
`RegWrite`	yeh instruction WB mein register likhegi
`Branch`	yeh instruction ek branch hai
`PCWrite`	Program Counter ko aage badhne do
`IF/ID_Write`	IF/ID latch ko update karne do

Topic ko yeh kyun chahiye: hazard unit ka poora output in signals mein se kuch hai. Stall karne ke liye, yeh PCWrite = 0 aur IF/ID_Write = 0 set karta hai (pipe ke front ko freeze karo) aur EX mein jaane wale control bits ko zero kar deta hai (ek bubble insert karo).

8. Logic symbols: $\land$ , $\lor$ , $==$

Parent mein formulas plain true/false logic hain. Teen symbols:

Toh scary-lagti load-use condition

MemRead \land ((ID/EX.Rd == IF/ID.Rs) \lor (ID/EX.Rd == IF/ID.Rt))

English mein padhte hain: "EX mein instruction ek load hai AND uska destination ID mein instruction ke kisi bhi source ke barabar hai." Yahi Figure 3 ki "abhi-ready-nahi" picture hai.

9. Bubble / NOP / stall / flush — chaar actions

Yeh sab topic mein kaise feed karta hai

Har box ek aisi cheez hai jo is page ne define ki. Arrows follow karo: hazard unit tab tak samajh nahi aayegi jab tak har upstream box sense na kare.

Equipment checklist

Khud ko test karo — right side cover karo aur reveal karne se pehle jawab do.

add $4, $2, $5 kya store karta hai, aur kahan?

$2 aur $5 ka sum, $4 mein store hota hai (sabse left = destination).

add $4, $2, $5 mein Rd, Rs, Rt kya hain?

Rd = 4, Rs = 2, Rt = 5.

Paanch pipeline stages ke naam order mein batao.

IF, ID, EX, MEM, WB.

Hazards exist kyun karte hain?

Kyunki pipeline instructions overlap karta hai — baad wali ek register read kar sakti hai jise pehli waali ne abhi likha nahi.

ID/EX.RegisterRd ka matlab kya hai?

ID/EX pipeline latch mein abhi baith rahi instruction ka destination register field (yani abhi EX mein hai).

MemRead = 1 tumhe instruction ke baare mein kya batata hai?

Yeh data memory read karta hai, yani yeh ek load hai.

A \land B

aur

A \lor B

translate karo.

\land

= AND (dono true);

\lor

= OR (kam se kam ek true).

Stall aur flush mein kya fark hai?

Stall = pause aur wait (data ready nahi). Flush = galat-fetched instruction cancel karo (taken branch).

Hazard logic $0 mein writes kyun ignore karta hai?

$0 hardwired to zero hai — isme "likhna" kuch nahi karta, isliye yeh kabhi real dependency create nahi kar sakta.

Jab upar har line instant ho, tab parent padhne jao: 5.2.10 Hazard detection units (Hinglish). Agle stops: 5.2.9-Forwarding-unit aur 5.2.11-Branch-prediction.