Foundations — Pipeline throughput and CPI

This page builds every piece of vocabulary the parent note Pipeline throughput and CPI leans on. We start from "what is a clock tick?" and stop only when you can read every symbol in the parent without pausing.

1. The clock and the clock period $T$

Look at the top of the figure below: the square wave rising and falling. The width of one full up-and-down box is $T$. Count how many boxes fit in one second, and that count is $f$.

Why the topic needs this. Every performance number in the parent — throughput, speedup — is ultimately "work done per second". Since the processor only does work on clock ticks, we must know how long a tick lasts. That is why $T$ appears in $\text{Throughput}=1/T$.

2. An instruction and its stages

To run one instruction the processor does several jobs in order. The classic split is 5 stages, each with a two-letter name:

In the figure below, one instruction is a horizontal strip cut into these 5 coloured blocks. Each block is one job. The delay of a stage is written as $t_i$ — the time that one job needs. The parent writes them as $t_1,t_2,\dots ,t_k$.

Why the topic needs this. The pipeline clock period is $T_{pipe}=\max (t_1,\dots ,t_k)+t_{reg}$. You cannot read that line unless you know that $t_i$ is a per-stage time and $t_{reg}$ is the hand-off cost.

3. max and Σ — two ways to combine the stage times

The parent uses two symbols that "fold a list of numbers into one number". They answer opposite questions.

The next figure shows the same five stage-bars twice: on the left, $\max$ points only at the tallest bar; on the right, $\Sigma$ stacks all bars end-to-end into one long bar.

4. Overlapping instructions — reading a pipeline diagram

Now put many instructions on the assembly line at once. Each instruction is a row; time runs left to right in clock ticks. Because station IF is free the moment instruction 1 moves to ID, instruction 2 can enter IF right behind it. The rows slide diagonally.

Read the figure carefully:

• The fill-up stretch is the first few ticks where the line is not yet full (only some stations busy).
• Once full, exactly one instruction finishes each tick — that is the whole point.
• Running $n$ instructions through a $k$-stage line takes $k+(n-1)$ ticks: $k$ ticks to push the first one all the way through, then one extra tick for each of the remaining $n-1$.

5. CPI, IPC and throughput — the three scoreboards

Now every symbol above lets us define the parent's headline quantities.

6. Hazards, stalls and bubbles — why real CPI is above 1

Why the topic needs this. The whole second half of the parent is about pushing ${\text{CPI}}_{actual}$ back down toward 1 — using forwarding to erase data stalls and better branch prediction to erase control stalls, and superscalar designs to push CPI below 1 entirely.

7. Speedup — comparing the two worlds

Notice this is exactly the "$\sum$ over $\max$" idea from Section 3 — now you can read the formula and know every symbol in it. This connects straight to raw CPU performance metrics.

Prerequisite map

Equipment checklist

Test yourself — reveal only after you have answered aloud.