Foundations — Pipeline throughput and CPI

5.2.9 · D1 · Hardware › Processor Datapath & Pipelining › Pipeline throughput and CPI

Yeh page wo har vocabulary piece build karta hai jis par parent note Pipeline throughput and CPI rely karta hai. Hum "clock tick kya hota hai?" se shuru karte hain aur tab tak rukenge nahi jab tak tum parent mein har symbol bina rukke read kar sako.

1. Clock aur clock period $T$

Neeche figure ke top pe dekho: square wave upar aur neeche ja rahi hai. Ek poore up-and-down box ki width $T$ hai. Count karo ki ek second mein kitne boxes fit hote hain, aur woh count $f$ hai.

Yeh topic ko kyun chahiye. Parent mein har performance number — throughput, speedup — ultimately "kaam kiya per second" hai. Kyunki processor sirf clock ticks par kaam karta hai, hume pata hona chahiye ki ek tick kitni der chalti hai. Isliye $T$, $\text{Throughput}=1/T$ mein appear karta hai.

2. Ek instruction aur uske stages

Ek instruction run karne ke liye processor order mein kai kaam karta hai. Classic split 5 stages ka hai, har ek ka do-letter naam hai:

Neeche figure mein, ek instruction ek horizontal strip hai jo in 5 coloured blocks mein kati hui hai. Har block ek kaam hai. Ek stage ki delay $t_i$ likhi jaati hai — woh time jo ek kaam ko chahiye. Parent unhe $t_1,t_2,\dots ,t_k$ likhta hai.

Yeh topic ko kyun chahiye. Pipeline clock period $T_{pipe}=\max (t_1,\dots ,t_k)+t_{reg}$ hai. Tum woh line tab tak nahi padh sakte jab tak tum nahi jaante ki $t_i$ per-stage time hai aur $t_{reg}$ hand-off cost hai.

3. max aur Σ — stage times combine karne ke do tarike

Parent do symbols use karta hai jo "numbers ki ek list ko fold karke ek number banaate hain". Woh opposite sawaalon ke jawab dete hain.

Agla figure wahi paanch stage-bars do baar dikhata hai: left par, $\max$ sirf sabse uunche bar ko point karta hai; right par, $\Sigma$ saare bars ko end-to-end ek lambe bar mein stack karta hai.

4. Instructions ko overlap karna — pipeline diagram padhna

Ab assembly line par ek saath bahut saare instructions rakho. Har instruction ek row hai; time left se right clock ticks mein chalta hai. Kyunki station IF us waqt free hai jab instruction 1 ID par move karta hai, instruction 2 iske bilkul peeche IF mein enter kar sakta hai. Rows diagonally slide karti hain.

Figure ko dhyaan se padho:

• Fill-up stretch pehle kuch ticks hain jahan line abhi puri nahi bhari (sirf kuch stations busy hain).
• Ek baar full hone par, bilkul ek instruction har tick finish hoti hai — yahi poora point hai.
• $n$ instructions ko $k$-stage line se run karne mein $k+(n-1)$ ticks lagte hain: pehle wali ko puri tarah push karne ke liye $k$ ticks, phir baaki $n-1$ mein se har ek ke liye ek extra tick.

5. CPI, IPC aur throughput — teen scoreboards

Ab upar diye har symbol se parent ki headline quantities define kar sakte hain.

6. Hazards, stalls aur bubbles — kyun real CPI 1 se upar hai

Yeh topic ko kyun chahiye. Parent ka poora doosra half ${\text{CPI}}_{actual}$ ko wapas 1 ki taraf push karne ke baare mein hai — forwarding use karke data stalls mitaao aur better branch prediction se control stalls mitaao, aur superscalar designs se CPI ko 1 se bhi neeche push karo.

7. Speedup — do duniyon ki comparison

Dhyaan do yeh exactly Section 3 ka "$\sum$ over $\max$" idea hai — ab tum formula padh sakte ho aur usmein har symbol jaante ho. Yeh directly raw CPU performance metrics se connect hota hai.

Prerequisite map

Equipment checklist

Khud test karo — sirf tab reveal karo jab tum zor se jawab de chuke ho.