Foundations — Data hazards and forwarding - bypassing

This page assumes you have seen the five-stage pipeline only in passing. We will rebuild every word, box, and arrow the parent note leans on, starting from absolute zero.

1. What is a register? (the boxes numbers live in)

Before any hazard can exist, we need a place where numbers are stored so instructions can read and write them.

Look at the figure: the three lockers coloured differently are the ones this one instruction touches. $R2$ and $R3$ are the sources (read from), $R1$ is the destination (written to). The whole wall of lockers together is called the register file.

2. Reading an instruction: destination and source

Every instruction we care about has the shape:

$\text{OP}\underset{\text{destination}}{\underbrace{R_d}},\underset{\text{source 1}}{\underbrace{R_s}},\underset{\text{source 2}}{\underbrace{R_t}}$

Why does the topic need these names? Because the hazard-detection rule is a comparison of roles across two instructions: "is the destination of the earlier one equal to a source of the later one?" You cannot state that without names for the roles.

The functions Destination(·) and Source(·)

3. The five stages (what a station does)

An instruction is not finished in one step. It walks through five stations, one per clock tick.

The two facts that create every hazard are circled in the figure:

• ID reads the source registers (early — stage 2).
• WB writes the destination register (late — stage 5).

So a number is needed early but delivered late. Hold that thought.

4. Which hazard are we even talking about? (RAW vs WAR vs WAW)

The parent note lists three flavours of data hazard. We only fix one of them on this page, so let's name all three so you know which shelf we're standing at.

5. Overlap: why several instructions run at once

Read the figure diagonally: at cycle 3, three different instructions occupy three different stages at the same time. This overlap is the whole point of pipelining — it is why it's fast. But it is also exactly why the number written in WB (cycle 5) can arrive after a later instruction already read the register in its ID (cycle 3). The overlap that gives speed also creates the RAW hazard.

6. Pipeline registers (the conveyor belts between stations)

How does a value computed in EX physically survive until WB, three ticks later? It sits in a buffer between the stations.

This is the key that unlocks forwarding. The answer is already sitting on a tray (EX/MEM or MEM/WB) long before it reaches the register file in WB. Forwarding is a wire that grabs the value off that tray and hands it straight back to the ALU.

7. The ALU and the multiplexer (where forwarding plugs in)

Look at the figure. Each ALU input has a MUX in front of it. Normally the MUX passes the value read from the register file. But when a hazard is detected, the forwarding unit flips the switch so the MUX instead passes the value grabbed off the EX/MEM or MEM/WB tray. That switch flip is forwarding. No MUX, no forwarding — you'd have nowhere to inject the shortcut value.

8. The logic symbols in the conditions

The parent note writes conditions using three symbols you must be able to read aloud.

Now we can write the RAW hazard condition in full, including every piece:

9. The load-use edge case (forwarding alone is not enough)

Everything above assumed the produced value exists at the end of EX — true for ALU ops. Loads are different, and this is the one case forwarding cannot fully rescue.

How these foundations feed the topic

The box below is a Mermaid diagram — a way of drawing a flow chart from text. Each A["..."] is a labelled box, and each --> is an arrow meaning "feeds into / is needed before". Read arrows as "you need the box at the tail before you can understand the box at the head".

Equipment checklist

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