Yeh page yeh assume karta hai ki aapne five-stage pipeline sirf passing mein dekha hai. Hum har word, box, aur arrow ko rebuild karenge jo parent note lean karta hai, bilkul absolute zero se shuru karke.
Koi bhi hazard exist karne se pehle, hume ek jagah chahiye jahan numbers store hon taaki instructions unhe read aur write kar sakein.
Figure dekho: teen alag-alag colour ke lockers woh hain jo yeh ek instruction touch karta hai. R2 aur R3sources hain (in se read kiya jaata hai), R1destination hai (isme likha jaata hai). Poori locker wall ko milake register file kehte hain.
Har instruction jis ke baare mein hum care karte hain uski yeh shape hoti hai:
OPdestinationRd,source 1Rs,source 2Rt
Yeh topic in names ki zaroorat kyun hai? Kyunki hazard-detection rule do instructions mein roles ki comparison hai: "kya pehli wali ka destination baad wali ke source ke barabar hai?" Aap yeh roles ke names ke bina state nahi kar sakte.
Parent note data hazard ke teen flavours list karta hai. Hum is page par sirf ek ko fix karte hain, toh chaliye teeno ko naam dete hain taaki pata chale hum kahan khade hain.
Figure ko diagonally padho: cycle 3 mein, teen alag instructions teen alag stages occupy kar rahi hain ek saath. Yeh overlap pipelining ka poora point hai — isliye yeh fast hai. Lekin yeh exactly wahi wajah bhi hai kyun WB (cycle 5) mein lika gaya number baad mein aa sakta hai jab ek baad wali instruction already ID (cycle 3) mein register read kar chuki ho. Jo overlap speed deta hai wahi RAW hazard bhi create karta hai.
EX mein compute ki gayi value WB tak, teen ticks baad, physically kaise survive karti hai? Woh stations ke beech ek buffer mein baith jaati hai.
Yahi woh key hai jo forwarding unlock karta hai. Answer already ek tray par rakha hua hai (EX/MEM ya MEM/WB) WB mein register file tak pahunchne se bahut pehle. Forwarding ek wire hai jo us tray se value grab karke seedha ALU ko wapas deti hai.
Figure dekho. Har ALU input ke aage ek MUX hai. Normally MUX register file se padhi gayi value pass karta hai. Lekin jab hazard detect hota hai, forwarding unit switch flip karti hai taaki MUX instead EX/MEM ya MEM/WB tray se grab ki gayi value pass kare. Wahi switch flip forwarding hai. MUX nahi, forwarding nahi — shortcut value inject karne ke liye koi jagah nahi hogi.
Upar sab kuch yeh assume karta tha ki produced value EX ke end par exist karti hai — ALU ops ke liye yeh sach hai. Loads alag hain, aur yeh woh ek case hai jahan forwarding poori tarah rescue nahi kar sakta.
Neeche wala box ek Mermaid diagram hai — text se flow chart draw karne ka ek tarika. Har A["..."] ek labelled box hai, aur har --> ek arrow hai jiska matlab hai "feed karta hai / iske pehle zaroori hai". Arrows padho jaise "aapko tail wala box samajhna zaroori hai head wale box se pehle".
Destination(i) = instruction i ka destination register number (Rd); Source(j) = instruction j ka ek source register number (Rs ya Rt).
Consumer ke liye hazard check do baar kyun karna padta hai?
Consumer ke do sources hain Rs aur Rt; pehle wali result dono mein se kisi ke bhi through aa sakti hai, isliye producer ke destination ko dono se compare karo.
Kaun se teen data-hazard types exist karte hain, aur is page mein kaunsa fix hota hai?
RAW, WAR, WAW — aur sirf RAW matter karta hai (aur fix hota hai) in-order 5-stage pipeline mein.
Full condition mein, RegWrite(i)=1 kiske against guard karta hai?
Ek aisi producer se false hazard ke against jo actually register write nahi karti (jaise store ya branch).
Equality ka ek test — "kya yeh value 1 hai?" (true/false) — assignment nahi.
Jab dono EX/MEM aur MEM/WB chahiye gaya register hold karein, kaunsa jeetega aur kyun?
EX/MEM jeetega, kyunki woh zyada recent result carry karta hai; forwarding unit pehle use check karta hai.
Load-use dependency mein forwarding ke saath bhi ek stall kyun lagta hai?
Load ka data sirf MEM ke end mein ready hota hai, agli instruction ke EX ke liye ek cycle bahut deri se, isliye forwarding se supply karne se pehle ek bubble unavoidable hai.