5.2.6 · D1 · HinglishProcessor Datapath & Pipelining

FoundationsData hazards and forwarding - bypassing

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5.2.6 · D1 · Hardware › Processor Datapath & Pipelining › Data hazards and forwarding - bypassing

Yeh page yeh assume karta hai ki aapne five-stage pipeline sirf passing mein dekha hai. Hum har word, box, aur arrow ko rebuild karenge jo parent note lean karta hai, bilkul absolute zero se shuru karke.


1. Register kya hota hai? (woh boxes jahan numbers rehte hain)

Koi bhi hazard exist karne se pehle, hume ek jagah chahiye jahan numbers store hon taaki instructions unhe read aur write kar sakein.

Figure — Data hazards and forwarding - bypassing

Figure dekho: teen alag-alag colour ke lockers woh hain jo yeh ek instruction touch karta hai. aur sources hain (in se read kiya jaata hai), destination hai (isme likha jaata hai). Poori locker wall ko milake register file kehte hain.


2. Ek instruction padhna: destination aur source

Har instruction jis ke baare mein hum care karte hain uski yeh shape hoti hai:

Yeh topic in names ki zaroorat kyun hai? Kyunki hazard-detection rule do instructions mein roles ki comparison hai: "kya pehli wali ka destination baad wali ke source ke barabar hai?" Aap yeh roles ke names ke bina state nahi kar sakte.

Functions Destination(·) aur Source(·)


3. Paanch stages (ek station kya karta hai)

Ek instruction ek step mein complete nahi hoti. Woh paanch stations se guzarti hai, ek station per clock tick.

Figure — Data hazards and forwarding - bypassing

Figure mein woh do facts circle ki gayi hain jo har hazard create karti hain:

  • ID reads karta hai source registers (jaldi — stage 2).
  • WB writes karta hai destination register (deri se — stage 5).

Toh ek number zaroori hota hai jaldi lekin deliver hota hai deri se. Yeh soch ke rakho.


4. Hum aakhir kaunse hazard ki baat kar rahe hain? (RAW vs WAR vs WAW)

Parent note data hazard ke teen flavours list karta hai. Hum is page par sirf ek ko fix karte hain, toh chaliye teeno ko naam dete hain taaki pata chale hum kahan khade hain.


5. Overlap: kai instructions ek saath kyun chalti hain

Figure — Data hazards and forwarding - bypassing

Figure ko diagonally padho: cycle 3 mein, teen alag instructions teen alag stages occupy kar rahi hain ek saath. Yeh overlap pipelining ka poora point hai — isliye yeh fast hai. Lekin yeh exactly wahi wajah bhi hai kyun WB (cycle 5) mein lika gaya number baad mein aa sakta hai jab ek baad wali instruction already ID (cycle 3) mein register read kar chuki ho. Jo overlap speed deta hai wahi RAW hazard bhi create karta hai.


6. Pipeline registers (stations ke beech conveyor belts)

EX mein compute ki gayi value WB tak, teen ticks baad, physically kaise survive karti hai? Woh stations ke beech ek buffer mein baith jaati hai.

Yahi woh key hai jo forwarding unlock karta hai. Answer already ek tray par rakha hua hai (EX/MEM ya MEM/WB) WB mein register file tak pahunchne se bahut pehle. Forwarding ek wire hai jo us tray se value grab karke seedha ALU ko wapas deti hai.


7. ALU aur multiplexer (jahan forwarding plug in hoti hai)

Figure — Data hazards and forwarding - bypassing

Figure dekho. Har ALU input ke aage ek MUX hai. Normally MUX register file se padhi gayi value pass karta hai. Lekin jab hazard detect hota hai, forwarding unit switch flip karti hai taaki MUX instead EX/MEM ya MEM/WB tray se grab ki gayi value pass kare. Wahi switch flip forwarding hai. MUX nahi, forwarding nahi — shortcut value inject karne ke liye koi jagah nahi hogi.


8. Conditions mein logic symbols

Parent note teen symbols use karke conditions likhta hai jinhe aapko aloud padhna aana chahiye.

Ab hum RAW hazard condition poori tarah likh sakte hain, har piece ke saath:


9. Load-use edge case (forwarding akela kaafi nahi)

Upar sab kuch yeh assume karta tha ki produced value EX ke end par exist karti hai — ALU ops ke liye yeh sach hai. Loads alag hain, aur yeh woh ek case hai jahan forwarding poori tarah rescue nahi kar sakta.


Yeh foundations topic ko kaise feed karte hain

Neeche wala box ek Mermaid diagram hai — text se flow chart draw karne ka ek tarika. Har A["..."] ek labelled box hai, aur har --> ek arrow hai jiska matlab hai "feed karta hai / iske pehle zaroori hai". Arrows padho jaise "aapko tail wala box samajhna zaroori hai head wale box se pehle".

Register and R0

Rd Rs Rt roles

Destination and Source lookups

Five stages IF ID EX MEM WB

Overlap of instructions

RAW hazard

Only RAW matters in order

Pipeline registers EX MEM and MEM WB

ALU with MUX inputs

Full hazard condition

Forwarding shortcut

EX MEM priority over MEM WB

Load use needs one stall


Equipment checklist

Khud test karo — sirf answer dene ke baad reveal karo.

Ek register kya store karta hai, aur ek baar mein kitne?
Ek number, ek tiny fast box mein; processor ke paas inका ek small fixed set hota hai (register file).
mein likhna kabhi hazard kyun cause nahi kar sakta?
hardwired hai zero ke liye, isliye isme write karna kuch real change nahi karta — koi baad wali instruction kabhi isse fresh data nahi leti.
Kaunsa stage source registers read karta hai, aur kaunsa stage destination write karta hai?
ID sources read karta hai (); WB destination write karta hai ().
Functions aur kya return karte hain?
= instruction ka destination register number (); = instruction ka ek source register number ( ya ).
Consumer ke liye hazard check do baar kyun karna padta hai?
Consumer ke do sources hain aur ; pehle wali result dono mein se kisi ke bhi through aa sakti hai, isliye producer ke destination ko dono se compare karo.
Kaun se teen data-hazard types exist karte hain, aur is page mein kaunsa fix hota hai?
RAW, WAR, WAW — aur sirf RAW matter karta hai (aur fix hota hai) in-order 5-stage pipeline mein.
Full condition mein, kiske against guard karta hai?
Ek aisi producer se false hazard ke against jo actually register write nahi karti (jaise store ya branch).
jaisi logic condition mein equals sign ka kya matlab hai?
Equality ka ek test — "kya yeh value 1 hai?" (true/false) — assignment nahi.
Jab dono EX/MEM aur MEM/WB chahiye gaya register hold karein, kaunsa jeetega aur kyun?
EX/MEM jeetega, kyunki woh zyada recent result carry karta hai; forwarding unit pehle use check karta hai.
Load-use dependency mein forwarding ke saath bhi ek stall kyun lagta hai?
Load ka data sirf MEM ke end mein ready hota hai, agli instruction ke EX ke liye ek cycle bahut deri se, isliye forwarding se supply karne se pehle ek bubble unavoidable hai.