Pipeline registers and control signals — Hinglish notes

5.2.4 · Hardware › Processor Datapath & Pipelining

Pipeline registers exist HI KYU karte hain?

YEH KYA HOTE HAIN: edge-triggered registers jo 5 classic stages ke beech rakhe jaate hain. Unhe do stages ke naam par rakha jaata hai jinke beech woh hote hain:

Register	Stages ke beech	Carry karta hai (data)
IF/ID	Fetch → Decode	instruction word, PC+4
ID/EX	Decode → Execute	reg values, sign-ext imm, PC+4, dest reg #
EX/MEM	Execute → Memory	ALU result, branch target, store data, dest reg #
MEM/WB	Memory → Write-back	memory data, ALU result, dest reg #

Note: WB ke baad koi register nahi hota — result register file mein likha jaata hai, jo khud hi stateful storage hai.

Figure — Pipeline registers and control signals

Control signals registers ke andar kyun travel karte hain?

EK signal kaise move karta hai: `RegWrite` ki life

Worked example

add $t0,$t1,$t2 ke liye RegWrite trace karna Step — ID: Control unit opcode 000000 padhti hai → RegWrite=1 set karti hai. Yeh step kyun? Kyunki opcode sirf ID mein visible hota hai; ek baar decide karo. Step — ID/EX mein latch karo: RegWrite=1 clock edge par ID/EX mein store hota hai. Kyun? WB abhi 3 cycles door hai; preserve karna zaroori hai. Step — EX→EX/MEM: EX RegWrite use nahi karta, toh woh usse unchanged EX/MEM mein copy karta hai. Kyun? Ek stage woh paperwork aage pass karta hai jo woh consume nahi karta. Step — MEM→MEM/WB: Abhi bhi unused, MEM/WB mein copy hota hai. Step — WB: RegWrite=1 finally register file ka write-enable drive karta hai. Ab kyun? Yahi woh jagah hai jahan destination register actually likha jaata hai. Result $t0 mein land karta hai.

Steel-manned mistakes

Recall Feynman: ek 12-saal-ke ko samjhao

Ek sandwich shop ki imagine karo jisme 5 workers ek line mein khade hain: ek bread leta hai, ek cheese lagata hai, ek grill karta hai, ek wrap karta hai, ek hand over karta hai. Har worker ke beech ek chhoti si tray hai. Jab ek worker finish karta hai, woh adha-bana sandwich aur ek sticky note jo batata hai aage kya karna hai tray par rakh deta hai. Agla worker tray uthata hai, note padhta hai, aur apna kaam karta hai. Yeh trays pipeline registers hain, aur sticky notes control signals hain. Is tarah 5 sandwiches ek saath ban rahe hote hain, aur koi nahi bhoolta kya karna hai — kyunki instructions sandwich ke saath travel karti hain!

Flashcards

Classic 5-stage MIPS pipeline mein kitne pipeline registers hote hain, aur 5 kyun nahi?

Chaar (IF/ID, ID/EX, EX/MEM, MEM/WB). WB ke baad koi register nahi kyunki WB register file mein likhta hai, jo already stateful storage hai.

Saare control signals kaunsi stage mein generate hote hain?

ID (Decode) mein, kyunki yahi woh akeli stage hai jo opcode dekhti hai.

Control signals pipeline registers ke andar kyun travel karte hain?

Kyunki RegWrite jaise signals stages baad mein use hote hain (WB), lekin opcode se sirf ID mein decode ho sakte hain; unhe aage transport karna padta hai.

Control signals ko kaun se teen bundles mein group kiya jaata hai?

EX bundle (ALUSrc, ALUOp, RegDst), MEM bundle (MemRead, MemWrite, Branch), WB bundle (RegWrite, MemtoReg).

Destination register number pipeline registers ke through kyun travel karta hai?

Kyunki WB tak instruction word chala gaya hota hai; 5-bit dest # carry kiye bina, WB galat register mein likhega.

ID/EX kya carry karta hai jo EX/MEM mein ab nahi hota?

EX control bundle (ALUSrc, ALUOp, RegDst) — woh EX mein consume hota hai aur baad mein drop ho jaata hai.

Kaunsa pipeline register ALU result aur store data carry karta hai?

EX/MEM.

PC+4 ko IF/ID ke aage kyun carry kiya jaata hai?

Kyunki branch target (PC+4 + imm<<2) baad mein EX mein compute hota hai, toh PC+4 ko us stage tak survive karna zaroori hai.

Ek control bundle ko uski stage consume karne ke baad kya hota hai?

Woh drop ho jaata hai aur agले pipeline register mein latch nahi hota (control ke liye har register pehle wale se narrow hota hai).

Connections

Single-cycle datapath — woh starting point jiske baad hum registers insert karte hain
Pipeline hazards — data/control hazards isliye aate hain kyunki signals aur results in registers ke across staggered hote hain
Forwarding and stalling — EX/MEM aur MEM/WB registers se directly values read karta hai
Control unit design — woh source jo ID mein saare bundles generate karta hai
Clocking and edge-triggered flip-flops — woh mechanism jo registers ko cleanly latch karne deta hai