Shuru karne se pehle, yahan wo words aur symbols hain jis par poora page tika hua hai. Inhe ek baar padh lo aur neeche ke traps automatically samajh aayenge.
Upar ki picture almost har trap ke peeche ka mental model hai: ek walled-off CPU jahan memory ke sirf do darwaaze hain — load aur store — aur ALU purely registers ki countertop par kaam karta hai.
Ab do performance words, kyunki aadhe traps speed compare karte hain.
Performance formula kahan se aati hai? Ise raw units se build karo, kuch memorize mat karo:
Neeche ki figure wohi cancellation draw karke dikhati hai — ise left se right padho aur dekho kaise "instruction" aur "cycle" units apne partners ko annihilate karte hain, sirf seconds bachte hain coral box mein. Jab bhi koi trap tumhe "sirf instructions count karo" bolne par majboor kare, yeh picture yaad karo: instruction count sirf teen mein se pehla box hai.
Aakhir mein, wo word jo explain karta hai kyun simpler instructions faster tick kar sakti hain:
Agli figure mein do rows compare karo. Top row ek simple load/store instruction hai: in → decode → ALU, ek chota coral double-arrow, toh tick brief ho sakti hai. Bottom row ek "fused read-modify-write" hai: in → decode → memory read → ALU, aur wo extra "memory read" stage coral double-arrow ko kaafi lamba khar deta hai, jo slower tick force karta hai. Traps mein le jaane wala takeaway: ek instruction mein stages add karna critical path ko lambaata hai aur Tclk ko har instruction ke liye upar kheenchta hai.
Number-heavy trap se pehle, humhe ek aur idea chahiye jis par parent note ne bina draw kiye lean kiya: pipeline ek slow memory miss ko kaise hide karta hai.
Figure ko cycles ka calendar samjho. Load (lavender) memory ka wait karte hue kai cycles stall karta hai, lekin independent ADD aur doosra load (mint) un idle cycles mein slide kar jaate hain bajaaye apni baari ka wait karne ke. Total wall-clock cycles ≈12 for 3 instructions ek average deta hai 4 cycles each — yahi exactly woh ≈12/3 = 4 hai jo parent ne quote kiya, aur isliye "ek load 10 cycles leta hai" ka matlab "CPI 10 hona chahiye" nahi hai.
Load/store ISA mein, ADD instruction ek memory address ko operand ke roop mein le sakta hai
False — puri baat yahi hai ki ALU instructions sirf registers dekhti hain; address ke liye pehle ek separate load chahiye. Ise allow karna wohi register-memory model recreate kar deta jise tum avoid kar rahe the.
Ek load/store program hamesha equivalent register-memory program se faster chalti hai
False — isme usually zyada instructions hoti hain; yeh total time mein tabhi jeetti hai jab lower CPI aur higher clock speed extra instruction count ko outweigh karein, har case mein nahi.
Load aur store load/store ISA mein ek memory address produce karne wali aadhi instructions hain
True — by definition memory ek "walled garden" hai; RAM ke andar ya bahar har trip ek explicit load ya store hai, isliye yahi address-generating operations hain.
"Register-register architecture" aur "load/store architecture" do alag cheezein hain
False — yeh ek hi design ke do naam hain; "register-register" yeh describe karta hai ki ALU ops register sources aur ek register destination lete hain.
Kyunki loads cache miss par ~10 cycles lete hain, load/store CPU ka average CPI lagbhag 10 hona chahiye
False — woh ~10 ek instruction ki latency hai, throughput CPI nahi; pipeline overlap independent work ko stall mein slide karta hai, isliye average CPI kaafi kam aata hai (parent ke example mein ≈4).
x86 ka kam instructions lena prove karta hai ki woh faster decode bhi karta hai
False — kam instructions lekin har ek zyada complex hai; ek register-memory ADD ek read-modify-write chhupata hai, jo ise longer decode aur variable latency deta hai — yahi hai jo iske clock speed ko cap karta hai.
32 registers hona 8 ki jagah sirf ek marketing number hai jiska koi real effect nahi
False — zyada registers intermediate results jaise (a+b) aur (c+3) ko on-chip rahne dete hain bajaaye slow memory mein spill hone ke, yahi cheez load/store ki explicit-data-movement style ko pay off karati hai.
Store instructions register se ek value read karke memory mein write karti hain
True — ek store register → memory move karta hai; yeh load ka mirror hai, aur yahi aakela tarika hai jisse ek computed result RAM mein wapas jaata hai.
Koi claim karta hai ki MIPS ko c = a[i] + b[i] ke liye x86 jaisi hi instruction count chahiye — yahan galti kahan hai?
MIPS ko 4 chahiye (do loads, ek add, ek store) versus real x86 ke 3 (MOV, ADD-from-memory, MOV — x86 bhi ek instruction mein do memory operands nahi padh sakta); extra explicit loads/stores walled-garden rule ka visible cost hai.
STR R6, R3 ; store R6 into R3 — misuse pakdo
Store ko ek memory address chahiye, likha jaata hai [R3], na ki bare register; STR R6, R3 ya toh syntax error hai ya register-to-register misread hai (jo stores nahi karte).
"Ek cycle bachane ke liye LDR R1,[R0]; ADD R2,R1,R3 ko ek fused ADD R2,[R0],R3 mein merge karo." Yeh ISA ke liye wrong optimization kyun hai?
Fused form ko ek naya encoding chahiye, cache miss par poori pipeline stall ho sakti hai, aur ISA ki regularity tooti hai — compiler iske bajaye latency hide karta hai load ko independent instructions se pehle reorder karke.
x86 ka MUL EAX, EBXEAX = EAX * EBX compute karne ke liye use kiya gaya — galti kya hai?
MUL ek one-operand instruction hai jo implicitly EAX use karta hai aur EDX:EAX likhta hai; do named registers ko ek mein multiply karne ke liye two-operand IMUL EAX, EBX use karna hoga.
Ek student ADD R1, R1, [mem] likhta hai "kyunki immediates allowed hain, toh memory bhi honi chahiye." Yahan confused reasoning kahan hai?
Ek immediate ek constant hai jo instruction word ke andar baki hoti hai, jisme koi memory trip nahi chahiye; ek memory operand ko actual RAM access chahiye, yahi cheez ALU instructions forbid karti hain — dono same type ke operand nahi hain.
Memory access ko sirf loads aur stores mein isolate karna doosri instructions ko faster aur more predictable kyun banata hai?
Kyunki non-memory instructions kabhi unpredictable cache ko touch nahi kar saktiein, unki timing fixed aur known hoti hai, isliye pipeline unhe schedule kar sakta hai cache hits ya misses ke baare mein guess kiye bina.
Load/store CPU often register-memory CPU se higher clock kyun kar sakta hai?
Iske simple, single-purpose instructions ka critical path chota hota hai (stage per kam logic), aur chote critical path se clock period Tclk drop hoti hai, yaani frequency fclk badhti hai.
Parent ke example mein ARM ke liye CPI ≈ 4 aur x86 ke liye 10 kyun milta hai jab dono ek hi slow memory hit karte hain?
ARM ki teen separate instructions pipeline ko memory miss overlap karne deti hain independent ADD ke saath, ≈12 cycles 3 instructions par spread karte hain; parent ka modelled x86 read-modify-write step apna internal read → modify → write overlap nahi kar sakta, isliye uske ≈10 cycles us ek step par land karte hain.
Load/store ISAs typically bahut saare registers kyun provide karti hain?
Kyunki intermediate results operations ke beech registers mein rehne chahiye (ALU unhe mid-computation memory mein stash nahi kar sakta), isliye zyada registers matlab RAM ko kam costly spills.
Out-of-order execution load/store machine par easier kyun hai?
Dependencies explicit aur simple hain — har instruction ek kaam named registers ke saath karta hai — isliye hardware clearly dekh sakta hai kaun si instructions independent hain aur unhe safely reorder kar sakta hai.
"Instructions count karo" do philosophies compare karne ka galat tarika kyun hai?
Performance T=I×CPI×Tclk se govern hoti hai; instruction count I teen factors mein se sirf ek hai, aur load/store ek higher I trade karta hai lower CPI aur shorter Tclk ke liye.
Ek immediate constant add karna (ADD R5, R4, #3) "registers only" rule violate karta hai?
Nahi — constant instruction encoding ke andar hi rehta hai, memory mein nahi, isliye koi memory access nahi hoti; ALU inputs effectively register-ya-baked-in rehti hain, kabhi memory address nahi.
Agar ek program bilkul memory use nahi karta (purely register data), toh use kitne loads/stores chahiye?
Zero — load/store rule sirf yeh mandate karta hai ki memory access loads aur stores se guzre; agar tum kabhi memory touch nahi karte, koi required nahi, aur formula ka Nloads+Nstores term 0 hai.
Agar program ko zaroorat se zyada registers hain (koi spilling nahi), load/store ke advantage ka kya hota hai?
Advantage apne sabse strong point par hai: koi register pressure nahi hone se, har intermediate on-chip rehta hai, isliye tum sirf essential loads/stores ke liye pay karte ho aur low-CPI, high-clock benefits poori tarah milti hain.
Ek aise program ke degenerate case mein jo sab memory traffic hai (har value ek baar use hoti hai), kya load/store phir bhi help karta hai?
Iska edge kam ho jaata hai kyunki ek loaded value ko kai ALU ops mein amortize nahi kar sakte — lekin ab dono machines same number of memory accesses par bottlenecked hain (har value ka ek read/write), isliye per-access cost decide karta hai; load/store ka shorter critical path phir bhi use un accesses ko utni hi tezi se clock out karne deta hai, aur successive independent loads/stores ko pipeline karna unke stall cycles overlap karta hai, isliye yeh register-memory se same memory-bound workload par peeche nahi padta.
Kya sirf ek instruction wala program, ADD R1, R2, R3, ek valid load/store program hai bhaale woh kabhi load ya store nahi karta?
Haan — "load/store architecture" describe karta hai ISA kya allow karta hai (memory sirf load/store se), na ki yeh requirement ki har program actually memory use kare; ek memory-free program bilkul legal hai.
Agar do loads back-to-back same address target karein, kya CPU ek ko reorder ya drop kar sakta hai?
Sirf tab jab memory consistency model allow kare (neeche definition dekho) — ek redundant load drop karna unsafe hai jab dusra core ya device us address par likh chuka ho, isliye hardware ek value tab hi reuse karta hai jab woh prove kar sake ki koi intervening write nahi hua.
Recall Quick self-test
T=I×CPI×Tclk mein teen symbols kya stand karte hain? ::: I = instructions ki sankhya, CPI = cycles per instruction, Tclk = clock period (seconds per tick); unka product total execution time seconds mein hai.
Is page par sabse bada reframe kya hai? ::: Time compare karo (T=I×CPI×Tclk), kabhi raw instruction count nahi — load/store zyada instructions trade karta hai lower CPI aur higher clock ke liye.
