RISC-V extensions (M, A, F, D, V, C) — Hinglish notes

5.1.8 · Hardware › Instruction Set Architecture (ISA)

The Six Standard Extensions

M Extension: Integer Multiplication and Division

Ye kyun exist karta hai: Multiplication ke liye dedicated hardware chahiye (Wallace trees, Booth encoders). Ek minimal CPU die area bachane ke liye ise omit karta hai. Lekin crypto, DSP, ya general compute ke liye, hardware multiply essential hai.

Worked example 64-bit Product Compute Karna

Task: 0x8000000 × 0x000002 (signed) multiply karo.

mul  t0, a1   # t0 = lower 32 bits = 0x000000
mulh t1, a0, a1   # t1 = upper 32 bits (signed) = 0xFFFFFFFF

Ye step kyun?

0x80000000 signed mein −2³¹ hai.
−2³¹ × 2 = −2³² = −4,294,967,296.
64-bit two's complement mein: 0xFFFFFFFF000000.
MUL extract karta hai [31:0] = 0x00000000, MULH extract karta hai [63:32] = 0xFFFFFFFF.

A Extension: Atomic Memory Operations

Ye kyun exist karta hai: Atomics ke bina, lock implement karne ke liye interrupts disable karne padte hain (user mode mein possible nahi) ya busy-waiting with race conditions. A extension compare-and-swap ko ek single hardware instruction banata hai.

Formula LR/SC (Load-Reserved / Store-Conditional)

lr.w rd, (rs1)        # Load word, address ko "reserved" mark karo
# ... naya value compute karo ...
sc.w rd, rs2, (rs1)   # rs2 store karo AGAR reservation abhi valid hai
                       # rd = 0 (success) ya 1 (failure)

First principles se derivation:

Problem: Do cores x read karte hain, increment karte hain, write back karte hain → ek update lost (race).
Solution: LR address ko per-core "reservation register" mein register karta hai.
Agar koi bhi doosra core us cache line pe write kare, reservation invalidate ho jaati hai.
SC tab succeed karta hai jab reservation abhi valid ho → atomicity guarantee karta hai.

Ye kyun kaam karta hai: Cache coherence protocols (MESI) already writes track karte hain. LR/SC us mechanism pe piggyback karta hai.

Worked example Lock-Free Increment

Task: Shared memory mein counter atomically increment karo.

retry:
    lr.w  t0, (a0)       # counter load karo, reserve karo
    addi  t1, t0, 1      # naya value compute karo
    sc.w  t2, t1, (a0)   # store karne ki koshish karo
    bnez  t2, retry      # Agar failed (t2 ≠ 0), retry karo

Ye step kyun?

lr.w counter load karta hai aur address mark karta hai.
Doosra core write karta hai → hamaari reservation break ho jaati hai.
sc.w 1 return karta hai (failure) → hum loop karte hain aur naye value ke saath retry karte hain.
Ye locks avoid karta hai lekin guarantee karta hai ki increment atomic hai.

F Extension: Single-Precision Floating-Point

Ye kyun exist karta hai: Floating-point math ke liye specialized units chahiye (exponent alignment, normalization). Ek tiny microcontroller ko ye nahi chahiye; ek graphics chip ko chahiye.

Worked example Floats Add Karna

Task: Hardware mein 1.5 + 0.25 compute karo.

flw  f0, 0(a0)        # Load 1.5 = 0x3FC00000
flw  f1, 4(a0)        # Load 0.25 = 0x3E800000
fadd.s f2, f0, f1     # f2 = 1.75 = 0x3FE00000

Ye step kyun (hardware internals)?

Unpack: Exponents aur mantissas extract karo.
- 1.5 = 1.1000... × 2⁰ (exp = 127, mantissa = 0.5)
- 0.25 = 1.0000... × 2⁻² (exp = 125, mantissa = 0.0)
Align: Chhote exponent ko bade se match karne ke liye shift karo.
- 0.25 = 0.0100... × 2⁰ (mantissa right 2 shift karo)
Mantissas add karo: 1.1000... + 0.0100... = 1.1100... (1.75)
Normalize: Already normalized hai.
Pack: Exp = 127, mantissa = 0.75 → 0x3FE00000.

D Extension: Double-Precision Floating-Point

Alag kyun? Kaafi embedded systems (audio codecs, sensors) ko sirf single-precision chahiye. Register width double karna silicon area aur power cost karta hai.

Worked example Double Kab Use Karein

Task: 1 million random floats sum karo.

float sum_single = 0.0f;   // Single-precision
double sum_double = 0.0;    // Double-precision
 
for (int i = 0; i < 1000000; i++) {
    sum_single += random_float();  // Precision lose hoti hai
    sum_double += random_float();  // Zyaada accurate
}

Ye kyun matter karta hai?

Har addition 23 bits (single) ya 52 bits (double) tak round hota hai.
10⁶ additions ke baad, single-precision error ≈ $1 0^{- 2}$ (sum ka 1%).
Double-precision error ≈ $1 0^{- 10}$ (negligible).

V Extension: Vector Operations

Ye kyun exist karta hai: Modern workloads (image processing, ML, physics) same operation arrays pe perform karte hain. Ek scalar CPU ek cycle mein ek element process karta hai; ek vector CPU ek cycle mein 4–64 elements process karta hai.

Worked example Vectorized Array Addition

Task: 1000 elements ke liye C[i] = A[i] + B[i].

li   t0, 1000          # Total elements
loop:
    vsetvli t1, t0, e32, m1   # vl = min(t0, max_elems) set karo, 32-bit elements
    vle32.v v0, (a0)           # A[i...i+vl-1] ko v0 mein load karo
    vle32.v v1, (a1)           # B[i...i+vl-1] ko v1 mein load karo
    vadd.vv v2, v0, v1         # v2 = v0 + v1 (element-wise)
    vse32.v v2, (a2)           # C[i...i+vl-1] store karo
 
    add  a0, a0, t1, 2         # A pointer vl*4 bytes aage badho
    add  a1, a1, t1, 2         # B pointer aage badho
    add  a2, a2, t1, 2         # C pointer aage badho
    sub  t0, t0, t1            # Remaining elements
    bnez t0, loop

Ye step kyun?

vsetvli poochhta hai: "Mere vector registers mein kitne elements fit honge?" Hardware t1 return karta hai (maybe 4, 8, ya 16).
vle32.v memory se t1 elements parallel mein load karta hai.
vadd.vv saare t1 pairs simultaneously add karta hai (ideal hardware pe ek cycle).
Loop tail handle karta hai: agar 1000 % 16 = 8, toh last iteration sirf 8 elements process karta hai.

C Extension: Compressed Instructions

Ye kyun exist karta hai: Instruction memory expensive hai (especially embedded systems pe). Agar ADDI x8, x8, 8 (har function epilogue mein use hota hai) 32 ki jagah 16 bits mein fit ho sake, toh ek typical program mein billions of bytes bach jaate hain.

Formula Encoding Rules

RVC (compressed) instructions bits [1:0] ≠ 11 use karte hain (32-bit instructions se distinguishable, jo hamesha [1:0] = 11 hote hain).
Common operations pe frequently-used registers (x8–x15, f8–f15) tak restricted.
Examples:
- C.ADD rd, rs2 (16-bit) ≡ ADD rd, rd, rs2 (32-bit)
- C.LWSP rd, offset(sp) (stack se load, 16-bit) ≡ LW rd, offset(sp) (32-bit)

Derivation: Hum sab instructions compress kyun nahi kar sakte?

Ek 32-bit instruction mein rd, rs1, rs2 ke liye 5-bit fields hain (32 registers).
Ek 16-bit instruction 3 × 5-bit = 15 bits ke register addresses (plus opcode) encode nahi kar sakta.
Solution: ABI convention kehta hai ki stack operations x2 (sp) use karte hain, function arguments x10–x17 (a0–a7) use karte hain. Ye patterns code mein dominate karte hain. Compressed forms common registers hardcode karte hain ya x8–x15 ke liye 3-bit fields use karte hain.

Worked example Compression Se Pehle Aur Baad Mein

Original (32 bits each):

addi sp, sp, -16     # Prologue: stack allocate karo
sw   ra, 12(sp)      # Return address save karo
lw   ra, 12(sp)      # Return address restore karo
addi sp, sp, 16      # Epilogue: stack deallocate karo
ret                  # Return (alias for jalr x0, 0(ra))

Compressed (16 bits each):

c.addi16sp sp, -16   # 16-bit
c.swsp ra, 12        # 16-bit (sp implicit)
c.lwsp ra, 12        # 16-bit
c.addi16sp sp, 16    # 16-bit
c.jr ra              # 16-bit return

Ye kyun matter karta hai?

Uncompressed: 5 instructions × 4 bytes = 20 bytes.
Compressed: 5 instructions × 2 bytes = 10 bytes (50% reduction).
Poore program mein, compression ~25% overall bachata hai (sab instructions compress nahi hote).

Extension Naming Convention

Recall Ek 12 Saal Ke Bachche Ko Samjhao

Socho tum Lego robots bana rahe ho. Base RISC-V kit (RV32I) mein sirf itne pieces hain ki ek robot chal sake. Lekin kya ho agar tum chahte ho ki tumhara robot:

Math homework jaldi kare → M extension add karo (multiplier gear).
Apne dost ke robot ko bina dhakka diye high-five kare → A extension add karo (atomic handshake).
Ude (air resistance calculate karna padega) → F/D extensions add karo (decimals ke liye calculator).
Painting kare (ek saath bahut saare pixels process karo) → V extension add karo (kaafi paintbrushes ek saath kaam karti hain).
Tumhari jeb mein fit ho → C extension add karo (instructions chhoti fold karo).

RISC-V tumhe sirf wo pieces khareedne deta hai jo chahiye. Ek chhota robot (smartwatch chip) flying aur painting parts skip karta hai. Ek bada robot (server CPU) ke paas sab kuch hota hai. Ye har robot ko saare possible attachments carry karne pe majboor karne se sasta aur zyaada efficient hai.

Connections

5.1.07-RISC-V-base-ISA — Extensions RV32I/RV64I base instructions pe build karte hain
5.2.03-IEEE-754-floating-point — F/D extensions ye standard implement karte hain
6.4.02-Cache-coherence-protocols — A extension LR/SC ke liye MESI pe rely karta hai
7.1.05-SIMD-and-vector-processors — V extension RISC-V ka vector architecture hai
3.3.06-Instruction-encoding — C extension 16-bit encoding variant use karta hai

#flashcards/hardware

RISC-V mein M extension kya add karta hai? :: Integer multiply (MUL, MULH) aur divide (DIV, REM) instructions. Iske bina, software ko shift-add loops se emulate karna padta hai (100× slow).

Teen MULH variants (MULH, MULHU, MULHSU) kyun hain?

Kyunki 32×32→64 multiplication ek two-part result produce karta hai. MULH (signed×signed), MULHU (unsigned×unsigned), aur MULHSU (signed×unsigned) upper 32 bits ke liye alag sign-extension requirements handle karte hain.

A extension mein LR.W kya karta hai?

Load-Reserved: ek word load karta hai aur address ko reservation register mein mark karta hai. Agar koi doosra core us cache line pe write kare, toh reservation invalidate ho jaati hai (SC.W ke zariye atomic compare-and-swap enable karta hai).

SC.W (Store-Conditional) atomicity kaise ensure karta hai?

Ye tab succeed karta hai jab LR.W ki reservation abhi valid ho. Success pe 0 return karta hai, failure pe 1. Agar doosra core address pe write kare, reservation break ho jaati hai aur SC.W fail karta hai, retry force karta hai.

F aur D extensions mein kya fark hai?

F 32-bit (single-precision) floating-point add karta hai; D 64-bit (double-precision) add karta hai. D ke liye wider register files chahiye (64-bit f0–f31) aur scientific computing ke liye zaroori hai jahan 23-bit mantissa (F) ki precision kaafi nahi hoti.

IEEE 754 exponent single ke liye 127 ya double ke liye 1023 se biased kyun hai?

Exponents ki unsigned integer comparison allow karne ke liye. Bias ke saath, bada exponent → bada biased value, signed comparison logic avoid karta hai. Bias = 2^(e-1) - 1 range ko symmetrically center karta hai.

V extension mein vsetvli kya karta hai?

"Vector set length immediate": vl (vector length) ko min(requested, max_elements) set karta hai. Hardware ka chosen actual vl return karta hai. Ye strip-mining loops enable karta hai jo un arrays handle karte hain jo vector width se evenly divisible nahi hain.

RISC-V ka V extension AVX-512 jaisi fixed ki jagah variable-length kyun hai?

Portability. Fixed-length sab implementations ko same register size rakhne pe majboor karta hai (chhoti chips ke liye mehenga). Variable-length (VLEN) ek phone chip ko 128-bit vectors aur ek server ko 2048-bit vectors use karne deta hai same software ke saath.

C extension se space savings kitni hai?

~25% code size reduction. Common instructions (stack operations, chhote immediates, frequent registers) 32 bits se 16 bits mein compress ho jaate hain. Sab instructions compress nahi hote, isliye 50% ki jagah 25%.

C extension 16-bit aur 32-bit instructions mein fark kaise karta hai?

Bits [1:0] se. C instructions [1:0] ≠ 11 rakhte hain (00, 01, 10). Standard 32-bit instructions hamesha [1:0] = 11 rakhte hain. Hardware in bits check karke decode karta hai.

"RV64GC" ka matlab kya hai?

RV64 (64-bit base) + G (general = IMAFD = Integer + Multiply + Atomics + single-Float + Double) + C (Compressed). Ye ek full-featured ISA ke liye common shorthand hai.

C extension sab instructions compress kyun nahi kar sakta?

Encoding space ki wajah se. 16 bits mein teen 5-bit register addresses (15 bits) plus opcode nahi aa sakta. Solution: sirf common patterns compress karo (sp-relative, a0–a7 arguments) ya x8–x15 ke liye 3-bit fields use karo (8 registers).

A extension mein AMOADD.W ka kya purpose hai?

Ek instruction mein atomic read-modify-write: mem[rs1] read karo, rs2 add karo, write back karo, old value return karo. Common atomic operations ke liye LR/SC loop (4 instructions) se faster hai.

V extension ko "strip-mining" loop kyun chahiye?

Kyunki array sizes hamesha vector width ke multiples nahi hoti. Strip-mining har iteration mein min(vl, remaining_elements) process karta hai, last iteration mein "tail" naturally handle karta hai jahan vl < max_elements hota hai.

MULH vs MUL kab use karein?

Arbitrary-precision arithmetic ke liye dono use karo. MUL lower 32 bits deta hai, MULH upper 32 bits deta hai. Mila ke, ye BigInt multiplication ya overflow detection ke liye poora 64-bit product banate hain.