Layout vs schematic (LVS) — Hinglish notes

4.2.9 · Hardware › VLSI Design

LVS exist kyun karta hai?

Teen sign-off checks physical verification mein:

DRC (Design Rule Check): Kya layout manufacturable hai? (spacing/width rules)
LVS (Layout vs Schematic): Kya layout intended circuit se match karta hai?
ERC (Electrical Rule Check): Kya koi electrical bugs hain? (floating gates, etc.)

LVS functional-equivalence ka sawaal answer karta hai, manufacturability ka nahi.

LVS precisely kya hai?

Do netlists equivalent hoti hain jab woh same labeled graph hoti hain:

Nodes = electrical nets (wires)
Edges/vertices = devices (transistors, R, C) apne terminals aur parameters ke saath

LVS kaise kaam karta hai? (first principles se derivation)

LVS engine ko do graphs build aur compare karne wala socho. Hum har stage derive karte hain.

Stage 1 — Layout extraction (layout graph banao)

Net formation (polygons par union-find). Har polygon ko apni net maan ke shuru karo. Nets merge karo jab:

do shapes same layer par overlap/abut karti hain, ya
do layers ki shapes ek contact/via se judi hain jahan woh layers connect hone allowed hain.

Yeh exactly ek union-find (disjoint-set) problem hai. Agar $N$ polygons hain aur $E$ overlap/via relations hain, toh sabhi nets label karne ka cost hai

$T_{connectivity} = O ((N + E) α (N))$

Yeh formula kyun? Union-find with path compression + union by rank, $E$ merges aur $N$ finds mein se har ek near-constant amortized time $α (N)$ mein karta hai (inverse Ackermann ≈ 4 kisi bhi real chip ke liye). Toh yeh essentially geometry mein linear hai.

Device recognition. Ek device overlapping layers ka ek pattern hai. Ek MOS transistor = poly crossing diffusion:

poly-over-diffusion overlap region gate/channel hai,
dono taraf ka diffusion = source aur drain,
underlying well ⇒ NMOS vs PMOS.

Gate width $W$ = poly–diffusion crossing edge ki length; length $L$ = current flow ke across poly dimension. Toh parameters seedha geometry se aate hain:

$W = (channel ki edge length), L = (channel ke across poly width) .$

Stage 1 ka output hai layout netlist: devices + extracted nets + $W / L$ .

Stage 2 — Reference netlist

Schematic compile hoti hai (ya ek SPICE netlist di jati hai) same graph form mein. Koi extraction nahi chahiye — connectivity already named hai.

Stage 3 — Graph matching (comparison)

Trick: coloring / partition refinement (Weisfeiler–Leman idea).

Har node ko ek initial color do local invariants se jo woh fake nahi kar sakta: ek net ke liye, jaise (#transistor gates us par, #sources, #drains, #passives). Ek device ke liye, uska type aur parameters.
Refine karo: har node ko neighbor colors ke multiset use karke recolor karo. Repeat karo.
Refinement ke baad, colors nodes ko classes mein partition karte hain. Do graphs mein classes match karo.
Agar dono graphs identical color histograms par converge karein aur har class ka unique pairing ho ⇒ LVS clean. Koi bhi leftover ambiguity/mismatch ⇒ ek discrepancy report karo.

Refinement $k$ chhote rounds chalati hai (jab tak stable na ho), har round $O (V + E)$ , toh practically

$T_{match} \approx O (k (V + E)),$

well-structured chips par near-linear (hierarchy bahut help karta hai — tum ek cell ek baar match karte ho aur reuse karte ho).

Typical LVS error classes (aur woh kaise dikhte hain)

Error	Physical cause	Graph symptom
Short	do nets touch karti hain jo nahi karni chahiye	do schematic nets ek layout net se map hoti hain
Open	wire tooti / via missing	ek schematic net do layout nets mein split hoti hai
Missing device	transistor place karna bhool gaye	device count mismatch
Parameter mismatch	galat $W / L$	isomorphic graph lekin $W / L$ differ karte hain
Property/label error	galat port/pin label	boundary par matching fail hoti hai

Worked examples

Worked example Example 1 — Ek CMOS inverter, LVS clean

Schematic: PMOS (source=VDD, gate=IN, drain=OUT), NMOS (source=GND, gate=IN, drain=OUT). Layout: ek poly line = IN dono ek n-diffusion (p-substrate mein) aur ek p-diffusion (n-well mein) ko cross karti hai.

Yeh step kyun? Single poly do diffusions cross karta hai ⇒ do gates jo dono net IN se connect hone chahiye — extraction poly polygon ko ek net = IN mein merge karti hai. ✔ "shared gate" se match.
Do inner diffusion regions ko join karne wala metal ⇒ ek net = OUT ke roop mein extract hota hai. ✔
p-diffusion outer contact VDD metal ko touch karta hai ⇒ PMOS source = VDD; n-diffusion outer contact GND ko touch karta hai ⇒ NMOS source = GND. ✔
Device count: dono mein 1 NMOS + 1 PMOS. Graph coloring ek unique bijection deta hai ⇒ LVS clean.

Common mistakes (steel-manned)

80/20 — woh 20% jo 80% deta hai

LVS = layout-netlist extract karo → schematic ke saath graph-compare karo.
Yeh devices + connectivity + parameters check karta hai, isomorphism se, name se nahi.
Main errors: short, open, missing/extra device, param mismatch.
DRC≠LVS≠ERC; LVS clean ≠ correct schematic.

Recall Feynman: ek 12-year-old ko explain karo

Socho tumhare paas LEGO instructions hain (schematic) aur woh model jo tumhare dost ne actually banaya (layout). LVS ek robot hai jo bane hue model ko dekhta hai, figure out karta hai ki kaun si bricks kaun si bricks se connect hain, aur check karta hai ki woh exactly instructions se match karta hai ya nahi. Agar tumhare dost ne accidentally do towers ek saath chipka di (short) ya do bricks click karna bhool gaya (open), toh robot chillata hai kaun sa piece galat hai — iska, sab kuch glue karne aur undo na kar paane se pehle.

LVS kya verify karta hai?

Ki extracted layout netlist schematic netlist ke saath graph-isomorphic hai — same devices, connectivity, aur parameters.

LVS ke do main stages kya hain?

(1) Layout extraction → layout netlist, (2) schematic netlist ke against graph comparison/matching.

LVS nets ko name se match kyun nahi kar sakta?

Layout nets auto-generated hoti hain (jaise N$27); matching graph structure (connectivity + device fingerprints) se honi chahiye, names se nahi.

Layout connectivity polygons se build karne ke liye algorithm kaunsa use hota hai?

Union-find (disjoint-set) overlapping/abutting shapes aur via-connected layers ko merge karta hai, ~O((N+E)·α(N)).

Extraction mein ek MOS transistor kaise recognize hota hai?

Poly crossing diffusion se — overlap gate/channel hai; dono taraf ka diffusion = source/drain; well type NMOS/PMOS deta hai.

Extraction mein W aur L kaise milte hain?

W = poly–diffusion crossing edge ki length; L = current flow ke along poly dimension.

DRC aur LVS mein kya fark hai?

DRC manufacturability check karta hai (spacing/width); LVS check karta hai ki layout intended circuit implement karta hai.

LVS mein ek short kaise dikhta hai?

Do schematic nets ek layout net se map hoti hain.

LVS mein ek open kaise dikhta hai?

Ek schematic net do layout nets mein split ho jati hai.

Kya LVS clean ho sakta hai lekin topology phir bhi galat sizes ke saath 'pass' ho?

Haan — parameter mismatch (jaise galat W/L) ek alag LVS discrepancy hai, chahe connectivity match kare.

Kya LVS clean chip ka correct function guarantee karta hai?

Nahi — yeh sirf prove karta hai ki layout diye gaye schematic ke barabar hai; ek buggy schematic phir bhi pass ho jati hai.

LVS mein graph matching ke neeche kaun si technique hai?

Iterative coloring / partition refinement (Weisfeiler–Leman style) local device/net invariants use karke.

Connections

Design Rule Check (DRC) — sibling physical-verification check (manufacturability).
Electrical Rule Check (ERC) — floating gates, over-driven nets.
Parasitic Extraction (PEX) — extraction ko R/C ke liye timing tak extend karta hai.
Netlist and SPICE — reference-netlist format.
CMOS Inverter Layout — canonical LVS example.
Union-Find (Disjoint Set) — connectivity engine.
Graph Isomorphism — matching ka theoretical core.
Physical Design Flow / Tape-out — sign-off mein LVS kahan aata hai.