This is the parent topic 's worked-example companion.
The parent gave you two formulas:
BW peak = W × ( 2 f ) × N , t CL = data rate (MT/s) 2 CL × 1 0 3 ns . every case those formulas can produce — including the weird, zero, and trick cases that break naive intuition. Nothing new is assumed; every symbol below is re-earned as it appears.
Intuition Before symbols: what the two formulasmean
W bytes cross the bus at once (a "width", like lanes on a road).f clock ticks per second (Hz). The data rate in MT/s (megatransfers/second) is 2 f DDR moves data on both the up-tick and down-tick of the clock.N independent buses (channels ) run in parallel.CL CAS Latency , the number of clock cycles the DRAM waits before the first byte of a column read appears. It's a count of ticks , not a time — so we convert it to nanoseconds.
Bandwidth is a rate (per second). Latency is a duration (a single wait). Keep those two pictures separate the whole way down.
Every problem this topic throws at you lands in exactly one of these cells. Each row below is covered by at least one worked example.
#
Case class
What's special
Covered by
C1
Standard bandwidth ordinary W , f , N
Ex 1
C2
Latency in ns convert CL cycles → time
Ex 2
C3
Equal-latency trap two kits, same ns, different MT/s
Ex 3
C4
Degenerate: N = 1 channels don't help
Ex 4
C5
Zero / limiting: f → 0 what happens as clock stalls
Ex 5
C6
Little's Law bridge how many bytes in flight to hit peak
Ex 6
C7
Real-world word problem "will this workload saturate the bus?"
Ex 7
C8
Exam twist: given BW, solve backwards invert the formula for an unknown
Ex 8
C9
Unit trap: clock vs data rate plugging f 2 f
Ex 9
Worked example DDR5-6400, 64-bit bus, dual channel. Peak bandwidth?Forecast: guess — is it above or below 100
Bytes per transfer: W = 64 bits = 8 bytes Why this step? One channel has 64 data wires; 8 bits = 1 byte, so 64/8 = 8 Data rate: DDR5-6400 means 2 f = 6400 MT/s = 6.4 × 1 0 9 Why? The "6400" is already the doubled figure — it's transfers, not the clock.Channels: N = 2 Why? Two buses fire at once, so their throughputs add .Multiply: BW = 8 × 6.4 × 1 0 9 × 2 = 1.024 × 1 0 11 B/s
BW = 102.4 GB/s
Verify: units check — bytes × ( transfers/s ) × ( channels ) = bytes/s 102.4 > 100
Worked example DDR5-6400 with CL32. Real latency in ns?Forecast: bigger MT/s number than DDR4 — do you expect latency smaller or about the same as older RAM? Guess.
True clock: f clk = 2 1 × 6400 = 3200 MHz = 3.2 × 1 0 9 Hz Why this step? Latency lives in clock cycles , and the real clock is half the MT/s number.Cycle time: T clk = 1/ f clk = 1/ ( 3.2 × 1 0 9 ) = 0.3125 ns Why? Period and frequency are reciprocals — one tick lasts 1/ f Multiply by CL: t CL = 32 × 0.3125 = 10.0 ns Why? CAS Latency is how many ticks we wait; each tick is T clk
t CL = 10.0 ns
Verify: using the shortcut t = 6400 2 ⋅ 32 × 1 0 3 = 6400 64 × 1000 = 10.0 same as the DDR4 kits in the parent note — proof that bandwidth soared while latency stood still (the CPU memory wall ).
Worked example Kit X: CL30 @ 6000 MT/s. Kit Y: CL36 @ 7200 MT/s. Which responds sooner?Forecast: Kit Y has the bigger MT/s and the bigger CL. Faster or slower? Commit before computing.
Kit X: t X = 6000 2 × 30 × 1 0 3 = 6000 60 × 1000 = 10.0 ns Why? Direct application of the ns formula.Kit Y: t Y = 7200 2 × 36 × 1 0 3 = 7200 72 × 1000 = 10.0 ns Why? Same formula, different numbers.Compare: t X = t Y = 10.0 identical response time .
Why does the bigger CL not lose? The higher frequency shrinks each cycle by exactly the ratio that the extra cycles add — they cancel.
t X = t Y = 10.0 ns
Verify: ratio check — 6000 30 = 7200 36 = 0.005 bandwidth (higher MT/s), so choose Y unless CL price matters. ✓
Worked example DDR4-3200, 64-bit,1 channel . Peak BW? Then compare to the dual-channel result.
Forecast: halve or unchanged versus the parent's 51.2
W = 8 = 3.2 × 1 0 9 N = 1 Why N = 1 Only one physical bus exists — no parallelism to add.BW = 8 × 3.2 × 1 0 9 × 1 = 2.56 × 1 0 10 B/s = 25.6 GB/s
BW N = 1 = 25.6 GB/s
Verify: exactly half of the parent's dual-channel 51.2 unchanged — N
Worked example Conceptual limit: asf → 0 Forecast: do both go to zero? Same rate? Think first.
Bandwidth: BW = W × ( 2 f ) × N f → 0 BW → 0 Why? Bandwidth is proportional to f Latency: t CL = CL / f clk f → 0 t CL → + ∞ Why? Cycle time 1/ f
Verify: look at the red latency curve — it shoots up (hyperbola t ∝ 1/ f BW ∝ f not the same quantity. ✓
BW = 102.4 L = 80 in flight to keep the bus 100% busy?
Forecast: hundreds of bytes? Thousands? Guess an order of magnitude.
Little's Law := BW × L Why this tool and not the BW formula alone? Peak BW is only reachable if enough requests overlap in time; Little's Law converts a rate + a delay into the concurrency needed.Plug in: 102.4 × 1 0 9 B/s × 80 × 1 0 − 9 s = 8192 bytes Why do the units work? ( B/s ) × ( s ) = bytes
8192 bytes in flight
Verify: 8192 = 128 ∼ 128 cache and prefetchers exist to raise this concurrency). ✓
Worked example A video filter streams a3840 × 2160 60 51.2 Forecast: comfortably yes, or dangerously close?
Bytes per frame (traffic): pixels = 3840 × 2160 = 8 , 294 , 400 2 × 4 = 8 = 8 , 294 , 400 × 8 = 66 , 355 , 200 bytes Why count both read and write? Both cross the memory bus and consume bandwidth.Per second: × 60 = 3.98 × 1 0 9 B/s ≈ 3.98 GB/s Why multiply by fps? Bandwidth is a per-second rate, so scale the per-frame traffic by frames per second.Compare to 51.2 required ≈ 3.98 7.8% Why the fraction? 3.98/51.2 = 0.0777
needs ≈ 3.98 GB/s < 51.2 GB/s (fits easily)
Verify: 66 , 355 , 200 × 60 = 3.981 × 1 0 9 3.981/51.2 = 0.0778
Worked example A datasheet claimsBW = 76.8 Forecast: which named DDR generation gives this?
Invert the formula: from BW = W × ( data rate ) × N data rate = W × N BW Why invert? The unknown moved into the denominator — algebraically isolate it.Plug in: data rate = 8 × 2 76.8 × 1 0 9 = 16 76.8 × 1 0 9 = 4.8 × 1 0 9 transfers/s = 4800 MT/s Why divide by W × N Bandwidth = width × rate × channels, so peeling off width and channels leaves the rate.
data rate = 4800 MT/s ( DDR5-4800 )
Verify: forward-check 8 × 4.8 × 1 0 9 × 2 = 76.8 × 1 0 9
Worked example Someone computes DDR4-3200 single-channel BW by plugging theclock 1600 Forecast: their answer will be off by what factor?
Wrong path: 8 × 1.6 × 1 0 9 × 1 = 12.8 GB/s Why is this tempting? "3200 = 2×1600", so they think 1600 is "the real speed".Correct path: the label 3200 already the data rate (2 f 8 × 3.2 × 1 0 9 × 1 = 25.6 GB/s Why? The DDR ×2 is baked into the MT/s number; applying it again (or using f
wrong = 12.8 GB/s , correct = 25.6 GB/s ( factor of 2 )
Verify: 25.6/12.8 = 2 25.6
Common mistake The two mistakes to never repeatNever use f MT/s already includes the ×2 (Ex 9).
Never expect channels to cut latency. N t CL
Recall Which cell was hardest for you?Ex 3 (equal-latency trap) ::: Bigger CL and bigger MT/s can cancel to the same ns — always convert to time.
Ex 5 (limiting) ::: As f → 0
Memory bandwidth and latency metrics — the parent topic these examples exercise.Memory channels and interleaving — the N DDR SDRAM generations — where the ×2 and MT/s labels of Ex 9 come from.Littles Law — the bridge worked in Ex 6.DRAM organization row buffer — the physical source of the CL latency in Ex 2.Cache hierarchy — why keeping many requests in flight (Ex 6) matters.CPU memory wall — Ex 2/3 show latency frozen while bandwidth climbs.