Foundations — Memory bandwidth and latency metrics

This page assumes you have seen nothing. We build every symbol the parent Memory bandwidth and latency metrics note leans on, one at a time, each earned before the next.

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1. Bit and Byte — the unit of "how much"

Figure 1 — one bulb is a bit; a row of eight bulbs is a byte.

Why the topic needs this: bandwidth is measured in bytes per second, so "bytes" is the stuff we are counting. If you do not know a byte is 8 bits, the "$64$ bits $=8$ bytes" step in Example 1 looks like magic. It is just $64÷8=8$.

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2. Bus and bus width $W$ — the "how many lanes"

Figure 2 — 64 wires carry 8 bytes in one transfer, so $W=8$; more lanes = more bytes per tick.

Why this symbol? The whole reason a wide bus gives more bandwidth is that more lanes move more bytes per tick. $W$ is the "width" half of "band-width". Look at Figure 2: doubling the lanes doubles the bytes per tick without changing how long any single bit takes to arrive.

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3. Second, frequency $f$, and hertz — the "how often"

Figure 3 — the faster clock (bottom) packs ticks closer, so its period $T$ is shorter.

Why the reciprocal, and why this tool? We use $T=1/f$ because latency is a time but hardware is quoted as a frequency. To turn "16 ticks of waiting" (CAS, see §8) into nanoseconds, we must know how many seconds one tick lasts — that is exactly $T$. Look at Figure 3: the faster clock packs its ticks closer, so each tick is shorter; that is why the same count of ticks can mean less time.

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4. Metric prefixes and scientific notation — reading the big/small numbers

Why the topic needs this: latency values like $10\text{ns}$ and bandwidths like $51.2\text{GB/s}$ are on wildly different scales; without prefixes the arithmetic in the worked examples is unreadable. Example: a "mega" count of $3200$ million transfers per second is $3200\times 10^6=3.2\times 10^9$ transfers/s. (We give the transfers-per-second idea its proper name, MT/s, in §6.)

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5. Rate — the idea behind "per second"

Why this is the whole bridge: the second form ($\text{amount}=\text{rate}\times \text{time}$) is Little's Law from Example 3: outstanding bytes $=$ bandwidth $\times$ latency $=B\times L$. If you understand "distance = speed × time", you already understand it.

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6. Transfer and data rate (MT/s) — and the DDR factor of 2

Figure 4 — each clock cycle has two edges (up + down); DDR fires one transfer on each, giving $2f_{\text{clk}}$.

Why this tool, the "edge"? We count edges, not whole cycles, because that is literally when DDR fires a transfer. Look at Figure 4: each full cycle has two edges (up, then down), so a $1600\text{MHz}$ DDR clock delivers $3200\text{MT/s}$. The name "DDR-3200" is already the doubled number — do not double it again.

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7. Channels $N$ — independent highways in parallel

Why $N$ multiplies bandwidth but not latency: adding a second highway lets twice as many cars pass per second (bandwidth $\times 2$), but any single car's trip time (latency) is unchanged — it still drives one highway end to end. This is exactly the parent's Forecast answer.

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8. CAS Latency (CL) — the count of cycles you wait

Why we define it here, before the formula: the parent quotes latency as "CL16" or "CL18". Because CL is measured in cycles, and a cycle's length $T_{\text{clk}}$ shrinks as $f_{\text{clk}}$ rises, two kits with different CL can still have the same real time. We need CL defined as a cycle-count first, then §9 converts it.

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9. Putting the symbols together

Now every symbol in the parent's formulas is defined. Before we combine them, name the two results we are building toward:

With those two names in hand, re-read the parent's formulas and nothing is unknown:

Here CL (from §8) is how many clock cycles you wait before the first byte — a pure count. Multiply a count of cycles by seconds-per-cycle ($T_{\text{clk}}$, from §3) and you get seconds, just like the reciprocal rule $T_{\text{clk}}=1/f_{\text{clk}}$.

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Prerequisite map

The figure below shows how each foundation feeds the next, ending in the two headline results.

Figure 5 — prerequisite map: bit → byte → width $W$, and second → frequency → edges → data rate, all flowing into bandwidth; period + CL flowing into latency.

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Equipment checklist