Blocking vs non-blocking assignments

3.5.4 · Hardware › HDL & Digital Design Flow

YEH distinction exist kyun karti hai?

HAR EK KYA karta hai (scheduling rule):

SCHEDULER actually isse kaise chalata hai (first principles)

Verilog simulation mein har time step par regions hote hain. Simplified:

1. Active region — blocking assignments evaluate aur apply karo; non-blocking assignments ki RHS evaluate karo aur result stash karo.
2. NBA (non-blocking) region — saare stashed non-blocking updates apply karo.

Worked Example 1 — Do registers swap karna (classic)

always @(posedge clk) begin
    a <= b;
    b <= a;
end

Kya hota hai? Edge par, pehle RHS sample hota hai: a ki nayi value = purana b, b ki nayi value = purana a. Phir dono update hote hain. Result: values swap hoti hain. ✔

Yeh step kyun? Kyunki <= line 2 mein purana a use karta hai, woh value nahi jo line 1 ne abhi assign ki.

Ab blocking ke saath:

always @(posedge clk) begin
    a = b;   // a becomes old b
    b = a;   // a is ALREADY b, so b = b  -> NO swap!
end

Yeh step kyun? = line 1 turant apply karta hai, isliye line 2 naya a dekhti hai. Dono end mein purana b ke barabar ho jaate hain. Yeh ek single flop plus ek wire synthesize karta hai — swap nahi.

Worked Example 2 — Pipeline / shift register

Goal: q1 -> q2 -> q3 har clock par shift kare.

always @(posedge clk) begin
    q3 <= q2;
    q2 <= q1;
    q1 <= d;
end

Yeh order se independent kyun kaam karta hai? Saare RHS (q2, q1, d) pre-edge values se sample hote hain, phir apply hote hain. Toh q3 ko purana q2 milta hai, wagera — ek sach mein 3-stage shift register. Teeno lines ko reorder karne par same hardware milega.

Blocking = ke saath (yahan galat):

q1 = d; q2 = q1; q3 = q2;   // q3 = q2 = q1 = d ALL in one clock -> collapses!

Yeh kyun fail hota hai? Turant updates d ko ek hi cycle mein q3 tak ripple kar dete hain → aapne ek flip-flop banaya, teen nahi.

Worked Example 3 — Combinational logic (blocking sahi hai)

always @(*) begin
    tmp = a & b;    // intermediate
    y   = tmp | c;  // uses just-computed tmp
end

Yahan blocking kyun? Yeh ek data-flow hai: tmp ready hona chahiye pehle, phir y use kare, bilkul gates mein ripple ki tarah. <= use karne par y purana tmp use karega, jo simulation mein galat/latched behaviour produce karega.

Golden Rules (80/20 — inhe memorize karo)

Common Mistakes (Steel-manned)

Active Recall

Connections

• Always blocks and sensitivity lists
• Combinational vs Sequential logic
• D Flip-Flops and Registers
• Race conditions in RTL simulation
• Synthesis vs Simulation mismatch
• Verilog data types (reg vs wire)
• Pipelining and shift registers

Concept Map