3.4.10 · D4Sequential Circuits

Exercises — Finite state machines (Mealy and Moore)

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Quick symbol refresher (so line one is readable):


Level 1 — Recognition

Exercise 1.1

On a state diagram you see a bubble drawn as — a 1 printed inside the bubble. Is this a Mealy or a Moore machine, and why?

Recall Solution

Moore. What we looked at: the output 1 is written inside the state bubble , attached to the state itself, not to any arrow. Why that settles it: Moore's output function is — it depends on the state only. A value that "belongs to a state" is exactly a Moore output. A Mealy output would be printed on a transition arrow as input / output, because also needs to know the input.

Exercise 1.2

An arrow between two states is labelled 1 / 0. What do the two numbers mean, and which machine type is this?

Recall Solution

Mealy, and the label reads input / output.

  • Left of the slash = the input symbol that causes this transition (here input 1).
  • Right of the slash = the output produced while taking this transition (here output 0). Why Mealy: the output is attached to the arrow, so it depends on both the state you left AND the input you read — that is , the Mealy signature.

Exercise 1.3

True or false: "A combinational circuit can remember how many 1s it has seen so far."

Recall Solution

False. Why: a combinational circuit's output depends only on the current inputs — it has no memory element. Remembering "how many 1s so far" requires storing information across clock cycles, which needs flip-flops. A circuit with memory is precisely a sequential circuit / FSM.


Level 2 — Application

Exercise 2.1

An FSM has states. How many flip-flops does the state register need?

Recall Solution

Use the encoding-width formula . What each piece means: each flip-flop stores one bit, so flip-flops give distinct patterns. We need at least one pattern per state: . Check: (too few), (enough). So 3 flip-flops. See State encoding for which code to assign each state.

Exercise 2.2

Take the "detect 11" sequence detector from Level 3 (the machine drawn in figure s01, which outputs 1 whenever the stream has just produced two consecutive 1s). It is built once as a Moore machine with 3 states () and once as a Mealy machine with 2 states (). How many flip-flops does each need? What's the surprise?

Recall Solution

Moore (3 states ): . Mealy (2 states ): . The surprise checked: going from 3 states to 2 states for this specific detect-11 machine does save a flip-flop (). But saving a state does not always save a flip-flop — see Exercise 2.3. The ceiling only "jumps" at powers of two.

Exercise 2.3

A design is reduced from 4 states to 3 states by State minimization. Does the flip-flop count drop?

Recall Solution

and . Answer: no — still 2 flip-flops. Why, walked through the ceiling step by step: the ceiling function holds one flat plateau for each whole-number output. Everything with rounds up to . Now and both sit inside that same window, so both land on the plateau value — the function does not "step down" between them. It only steps to a lower plateau () once , i.e. when . So dropping 4→3 stays on plateau 2; only 3→2 would fall to plateau 1. The minimization may still save combinational logic (fewer transitions to decode), just not registers.


Level 3 — Analysis

The figure below draws the same "detect 11" example both ways so you can trace it. Use it directly while solving 3.1 and 3.2. Note the "reset" arrow coming from nowhere into (top) and into (bottom): that marks the initial state .

Figure — Finite state machines (Mealy and Moore)

Exercise 3.1

Run the Moore "detect 11" machine on input 1 1 1 0. Give the state sequence and the output stream. States: (reset, out 0), (out 0), (out 1); on 0, on 1 advance .

Recall Solution

Start in the reset state (the one with the incoming "reset" arrow). Moore rule: the output printed is the output of the state you are currently in, read before the next input moves you.

Step Current state Output (of current state) Input read Next state
0 (reset) 0 1
1 0 1
2 1 1
3 1 0
4 0

Output stream: 0 0 1 1 0. Why there is a step 4 (an output with no input): a Moore output is read from the state you are sitting in, and after consuming the 4th input (0) you land in a new state . That landing is itself observable — the machine now is in and shows 's output 0. So inputs walk you through occupied states, and Moore emits one symbol per occupied state ⇒ output symbols. Step 4 is the output of the final landing state, not a phantom. Reading the timing: the first 1 in the output appears at step 2 — one cycle after the second input 1 (the 11 completed between step 1 and step 2). Then the third input 1 keeps us in , so we output 1 again. This "one cycle late, then held" is the Moore timing fingerprint.

Exercise 3.2

Run the Mealy version on the same input 1 1 1 0. States (reset, no 1), (one 1); transitions: 0/0→, 1/0→, 0/0→, 1/1.

Recall Solution

Start in reset state (incoming "reset" arrow). Mealy rule: the output is produced on the transition arrow, so it is decided by the (current state, input) pair — read the output as you take the step.

Step State Input Output (on arrow) Next state
0 (reset) 1 0
1 1 1
2 1 1
3 0 0

Output stream: 0 1 1 0. Compare to Moore's 0 0 1 1 0: Mealy fires 1 at step 1 — the same cycle the second 1 arrives, one cycle earlier than Moore. Also note Mealy produces exactly one output per input (one symbol per arrow taken), so 4 inputs give 4 outputs; Moore gave 5 because it also emits from the final landing state (see 3.1). That "one extra symbol" is a Moore-vs-Mealy bookkeeping difference, not a difference in what is detected.

Exercise 3.3

Look at Clocking and timing behaviour: input 1 is held steady and then, mid-cycle, glitches briefly to 0 and back to 1. Which machine's output can flicker, and why?

Recall Solution

The Mealy output can flicker; the Moore output cannot. Why: in a Mealy machine the input wire feeds directly into the output logic (). If momentarily dips to 0, the combinational output re-evaluates immediately and momentarily drops — a glitch. In a Moore machine the output depends on only; is stored in a flip-flop and changes only on a clock edge. A mid-cycle input glitch never reaches the output logic, so the output stays rock-steady until the next edge. This is exactly why Moore is called glitch-free / synchronous.


Level 4 — Synthesis

Exercise 4.1

Design a Moore machine that outputs 1 exactly when the input stream ends in the pattern 10 (a 1 followed immediately by a 0). Give states with their meanings, mark the reset state, the transition table, and the output column.

Recall Solution

Step 1 — What must each state remember? To know if we just saw 10, we must track: have we seen a 1 that could start the pattern?

  • (reset): "no 1 pending" (start) — output 0
  • : "last bit was 1" — output 0
  • : "just completed 10" — output 1

Step 2 — Fill by asking, for each state, where do 0 and 1 send me? (The reset state is the one with the incoming "reset" arrow when drawn.)

State in=0 → in=1 → output
(reset) 0
0
1

Why these arrows:

  • From (a 1 is pending) a 0 completes 10 → go to . A 1 keeps a fresh pending 1 → stay .
  • From a 1 starts a new possible pattern → ; a 0 breaks it (00 has no pending 1) → .

Step 3 — Flip-flops: .

Test on 1 0 1 0 (starting in reset ): . Outputs read from current state each step: 0 0 1 0 1. The 1s land the cycle after each 10 completes — correct Moore timing. See Sequence detectors.

Exercise 4.2

Redesign the 10 detector as a Mealy machine. How many states now, and what is the table? Mark the reset state.

Recall Solution

Key idea: the "completing 0" can be tested on the transition, so we don't need a dedicated state — we fold it into an arrow label.

  • (reset): "no 1 pending" (start)
  • : "last bit was 1"
State in=0 (next / out) in=1 (next / out)
(reset) / 0 / 0
/ 1 / 0

Why the 1 sits on 0: being in means "a 1 is pending"; reading a 0 right now is the completion of 10, so we emit 1 on that very transition, then land back in .

Flip-flops: . Test on 1 0 1 0 (starting in reset ): —1/0→—0/1—1/0→—0/1. Output 0 1 0 1. Fires the same cycle the completing 0 arrives — Mealy is one cycle earlier and uses one fewer state (2 vs 3) and one fewer flip-flop (1 vs 2).


Level 5 — Mastery

Exercise 5.1

Design a Mealy FSM for a serial two's-complement (2C) negator: bits arrive LSB first; output the 2C negation of the input stream. Rule you may use: scan from LSB, copy bits unchanged up to and including the first 1, then invert every bit after that. Give states, mark the reset state, give the table, and trace 1 0 1 1 (LSB first).

Recall Solution

Step 1 — What must be remembered? Only one fact: "have we passed the first 1 yet?" That's a single bit of memory ⇒ two states.

  • (reset, copy mode): still looking for the first 1; pass input through unchanged.
  • (invert mode): first 1 already seen; invert everything from now on.

Step 2 — Mealy table (output on the arrow, decided by state + current bit):

State in=0 (next / out) in=1 (next / out)
(reset, copy) / 0 / 1
(invert) / 1 / 0

Why each entry:

  • , read 0: haven't hit the first 1 yet, copy it (out 0), stay copying.
  • , read 1: this is the first 1 — still copied unchanged (out 1), but now switch to invert mode ().
  • , read 0: invert → out 1. , read 1: invert → out 0.

Step 3 — Trace 1 0 1 1 (LSB first). Start in reset :

Step State In Out Next
0 (reset) 1 1
1 0 1
2 1 0
3 1 0

Output (LSB first): 1 1 0 0. Sanity check as numbers. Input LSB-first 1 0 1 1 is the value , i.e. 1101 as a 4-bit unsigned = the signed value in 4-bit 2C. Its negation is = 0011 = LSB-first 1 1 0 0. ✓ Matches our output stream exactly. Flip-flops: .

Exercise 5.2

Convert the Moore detect 11 machine ( with outputs ; reset ) into a Mealy machine using the fewest states, show the merged 2-state table (mark the reset state), and prove the output timing shifts by exactly one cycle by running both on input 0 1 1 0 1.

Recall Solution

Merge rule (Moore→Mealy): a Moore output that "lives in" a landing state can instead be emitted on every arrow that enters that state. In the Moore machine, state (output 1) is entered by exactly two arrows: " on input 1" and " on input 1". So we label those two arrows with output 1; then no longer needs its own output identity and can merge with 's "one 1 already pending" role.

Resulting 2-state Mealy machine ( = "no pending 1", reset; = "one 1 pending"):

State in=0 (next / out) in=1 (next / out)
(reset) / 0 / 0
/ 0 / 1

Why this is minimal: the only reason Moore needed a third state was to hold the "detected" output value. Once the detection is answered by looking at the current input on a transition, that third state has no remaining job and disappears. Two states is the floor because we still must distinguish "did the previous bit leave a pending 1?" — one genuine bit of memory.

Timing proof on 0 1 1 0 1:

Moore run (output = current-state output; inputs ⇒ 6 occupied states ⇒ 6 symbols), start in reset :

Step State Out In Next
0 (reset) 0 0
1 0 1
2 0 1
3 1 0
4 0 1
5 0

Moore output: 0 0 0 1 0 0.

Mealy run (output on each arrow; 5 inputs ⇒ 5 symbols), start in reset :

Step State In Out Next
0 (reset) 0 0
1 1 0
2 1 1
3 0 0
4 1 0

Mealy output: 0 0 1 0 0.

Reading the shift: the Mealy 1 occurs at step 2 — the exact transition that reads the second 1 of the 11. The Moore 1 occurs at step 3 — one cycle later, when the machine has landed in . Align both to the input that triggered them and they mark the identical 11 position; the only difference is Moore's one-cycle registration delay (plus its one extra final-landing symbol). This confirms the Mealy/Moore boundary is timing, not behaviour.


Connections

  • Parent: Mealy & Moore FSMs — the definitions these exercises drill
  • Sequence detectors — Exercises 3–4 are canonical detectors
  • State minimization — Exercise 2.3's flip-flop-count reasoning
  • State encoding — assigning binary codes once you know
  • Clocking and timing — Exercise 3.3's glitch analysis
  • Flip-flops — the registers counted by
  • Combinational Logic — builds the and blocks in every design above