Worked examples — Comparators

Before anything, some words and symbols we will reuse. If you have not met them, read them slowly:

---

The scenario matrix

Every comparator problem lives in exactly one of these cells. Our examples below are labelled by cell so you can see the whole space is covered.

Cell	What happens	Which rule fires	Example
C1	1-bit, all four rows	raw $G,L,E$	Ex 1
C2	Multi-bit, MSB alone decides	$A_{n-1}{\bar{B}}_{n-1}$ term	Ex 2
C3	Multi-bit, MSBs tie → LSB decides	guard $x_{n-1}$	Ex 3
C4	Full equality (every bit matches)	$E=x_{n-1}\cdots x_0$	Ex 4
C5	Extreme inequality — $A$ all 0s vs $B$ all 1s (and the mirror $A$ all 1s vs $B$ all 0s)	limiting case, both directions	Ex 5
C6	The $1000$ vs $0111$ trap (MSB beats many low 1s)	MSB-first proof	Ex 6
C7	Degenerate guard — what if you forget $x_i$?	contradiction demo	Ex 7
C8	Cascaded 7485, local tie → pass-through	$(A>B{)}_{out}=G_{loc}+E_{loc}\cdot (\cdot {)}_{in}$	Ex 8
C9	Cascaded, local decides → cascade ignored	pass-through blocked	Ex 9
C10	Word problem (threshold / real world)	applied	Ex 10

We will keep re-using the 2-bit equations from the parent (remember every "$+$" here is OR): $E=x_1{x}_0,G=A_1{\bar{B}}_1+x_1{A}_0{\bar{B}}_0,L={\bar{A}}_1{B}_1+x_1{\bar{A}}_0{B}_0$

---

Example 1 — the 1-bit engine, all four rows (Cell C1)

Forecast: guess which single output is high for $(A,B)=(1,0)$ before reading on.

1. Row $(0,0)$. $G=0\cdot \bar{0}=0\cdot 1=0$; $L=\bar{0}\cdot 0=0$; $E=\overline{0\oplus 0}=\overline{0}=1$. So $E=1$. Why this step? We must test the "both zero" degenerate case — equal numbers still count.
2. Row $(0,1)$. $G=0\cdot \bar{1}=0$; $L=\bar{0}\cdot 1=1$; $E=\overline{0\oplus 1}=\overline{1}=0$. So $L=1$. Why? This is the only "$A$ smaller" 1-bit case; it must light exactly $L$.
3. Row $(1,0)$. $G=1\cdot \bar{0}=1$; $L=\bar{1}\cdot 0=0$; $E=\overline{1\oplus 0}=0$. So $G=1$. Why? The forecast answer — $A=1>B=0$, greater must fire alone.
4. Row $(1,1)$. $G=1\cdot \bar{1}=0$; $L=0$; $E=\overline{1\oplus 1}=\overline{0}=1$. So $E=1$. Why? This is the "both one" case — the second way two bits can be equal, so $E$ must fire just like row $(0,0)$.

Verify: count how many outputs are high per row (this "$+$" is an arithmetic count, not Boolean OR) — row $(0,0)$: $0+1+0$; row $(0,1)$: $0+0+1$; row $(1,0)$: $1+0+0$; row $(1,1)$: $0+1+0$ — every count is $1$, so exactly one output fires each row. The law $G+E+L=1$ holds. ✔ (See Truth Tables and Minterms for reading these off.)

---

Example 2 — MSB alone decides (Cell C2)

Forecast: $2>0$, so guess $G=1$ — but prove the LSB term never even gets a chance to speak.

Here $A_1=1,A_0=0,B_1=0,B_0=0$ ($A_1,B_1$ are the MSBs; $A_0,B_0$ the LSBs).

1. Guards. $x_1=\overline{A_1\oplus B_1}=\overline{1\oplus 0}=\overline{1}=0$. $x_0=\overline{0\oplus 0}=1$. Why this step? $x_1=0$ is the whole story: the MSBs differ, so no lower term will be allowed through.
2. Greater. $G=A_1{\bar{B}}_1+x_1{A}_0{\bar{B}}_0=1\cdot 1+0\cdot (0\cdot 1)=1+0=1$ (the "$+$" here is OR). Why? First term fires from the MSB. The second term is multiplied by $x_1=0$, so it is dead — exactly what we wanted.
3. Less & Equal. $L={\bar{A}}_1{B}_1+x_1(\dots )=0\cdot 0+0=0$. $E=x_1{x}_0=0\cdot 1=0$.

Verify: count of high outputs $=1+0+0=1$ ✔. And $2>0$ ✔. The MSB decided; the LSB was irrelevant.

The figure below shows this exact case: the shaded region marks the LSB column that the guard $x_1=0$ switches off, and the orange arrow shows the MSB making the decision alone.

---

Example 3 — MSBs tie, LSB breaks the tie (Cell C3)

Forecast: the top bits match, so the guard $x_1$ must open the gate and let the LSB decide. Guess the winner.

Here $A_1=0,A_0=1,B_1=0,B_0=0$.

1. Guards. $x_1=\overline{0\oplus 0}=1$ (MSBs match — gate is open). $x_0=\overline{1\oplus 0}=\overline{1}=0$. Why this step? $x_1=1$ is the permission slip that lets the LSB term act.
2. Greater. $G=A_1{\bar{B}}_1+x_1{A}_0{\bar{B}}_0=0\cdot 1+1\cdot (1\cdot \bar{0})=0+1\cdot 1=1$. Why? First term is $0$ (MSBs equal, nobody wins there). Second term survives because $x_1=1$, and $A_0{\bar{B}}_0=1\cdot 1=1$ says the LSB of $A$ beats $B$.
3. Less & Equal. $L={\bar{A}}_1{B}_1+x_1{\bar{A}}_0{B}_0=0+1\cdot (0\cdot 0)=0$. $E=x_1{x}_0=1\cdot 0=0$.

Verify: count of high outputs $=1$ ✔; $1>0$ ✔. This is the pure LSB-tiebreak case — contrast it with Ex 2 where the LSB never mattered.

Compare the figure below with the one from Ex 2: here the MSBs match, so the guard $x_1=1$ opens the gate (no shaded dead column), and the orange arrow now points at the LSB column, which is where the decision actually happens.

---

Example 4 — full equality (Cell C4)

Forecast: equal numbers — guess which single output is high and which two are zero.

1. Guards. $x_1=\overline{1\oplus 1}=\overline{0}=1$; $x_0=\overline{1\oplus 1}=1$. Why this step? Both flags are $1$ — this is what "every bit matches" looks like numerically.
2. Equal. $E=x_1{x}_0=1\cdot 1=1$. Why? Equality requires all guards high; the AND of them lights $E$.
3. Greater. $G=A_1{\bar{B}}_1+x_1{A}_0{\bar{B}}_0=1\cdot \bar{1}+1\cdot (1\cdot \bar{1})=1\cdot 0+1\cdot 0=0$. Why? ${\bar{B}}_1=0$ and ${\bar{B}}_0=0$ kill both greater-terms — no bit of $A$ is strictly above $B$.
4. Less. By the same mirror logic $L=0$.

Verify: count of high outputs $=0+1+0=1$ ✔; $3=3$ ✔. Equality is the AND-of-guards — remember XNOR, not XOR (see the trap in Ex 7).

---

Example 5 — the extreme inequality, both directions (Cell C5)

Forecast: the smallest vs the largest, then flipped. Guess which output fires in each, and whether the MSB alone settles it both times.

(a) $A=00,B=11$.

1. Guards. $x_1=\overline{0\oplus 1}=0$; $x_0=\overline{0\oplus 1}=0$. Both gates shut. Why this step? Every bit differs — the guards confirm there is no tie anywhere.
2. Less. $L={\bar{A}}_1{B}_1+x_1{\bar{A}}_0{B}_0=\bar{0}\cdot 1+0\cdot (\dots )=1\cdot 1+0=1$. Why? The MSB term ${\bar{A}}_1{B}_1=1$ alone fires; $x_1=0$ disables the LSB term (which would also have said "less", but we never need it).
3. Greater & Equal. $G=A_1{\bar{B}}_1+x_1(\dots )=0\cdot 0+0=0$. $E=x_1{x}_0=0\cdot 0=0$.

Verify (a): count of high outputs $=0+0+1=1$ ✔; $0<3$ ✔.

(b) $A=11,B=00$ — the mirror.

1. Guards. $x_1=\overline{1\oplus 0}=0$; $x_0=\overline{1\oplus 0}=0$. Both gates shut again.
2. Greater. $G=A_1{\bar{B}}_1+x_1{A}_0{\bar{B}}_0=1\cdot 1+0=1$. Why? Now the MSB of $A$ is $1$ above $B$'s $0$, so the top greater-term fires alone.
3. Less & Equal. $L={\bar{A}}_1{B}_1+x_1(\dots )=0\cdot 0+0=0$. $E=x_1{x}_0=0$.

Verify (b): count of high outputs $=1+0+0=1$ ✔; $3>0$ ✔. Both extremes: only the MSB term does the work — a preview of the trap in Ex 6.

---

Example 6 — the $1000$ vs $0111$ trap (Cell C6)

Forecast: count the 1s if you like — then watch the MSB overrule the count entirely.

The 4-bit greater equation (from parent §3; every "$+$" below is OR): $G=A_3{\bar{B}}_3+x_3{A}_2{\bar{B}}_2+x_3{x}_2{A}_1{\bar{B}}_1+x_3{x}_2{x}_1{A}_0{\bar{B}}_0$

1. Top guard. $x_3=\overline{A_3\oplus B_3}=\overline{1\oplus 0}=\overline{1}=0$. Why this step? The MSBs differ. That single $0$ multiplies every lower term to zero — the low three 1s of $B$ are silenced before they can vote.
2. First term. $A_3{\bar{B}}_3=1\cdot \bar{0}=1\cdot 1=1$. So $G=1+(0\cdot \dots )=1$. Why? $A$'s MSB is $1$ while $B$'s is $0$: magnitude is settled at the top digit, exactly like humans comparing $3746$ vs $3699$.
3. Cross-check Less. $L$'s MSB term is ${\bar{A}}_3{B}_3=\bar{1}\cdot 0=0$, and every lower $L$-term is guarded by $x_3=0$ → all dead → $L=0$.

Verify: count of high outputs $=1+0+0=1$ ✔; $8>7$ ✔. The "count the 1s" instinct is wrong — the highest differing bit rules. This is the LSB-first trap warned about in the parent's §6; contrast with a Ripple Carry Adder which genuinely goes LSB-first.

---

Example 7 — degenerate guard: what forgetting $x_i$ breaks (Cell C7)

Forecast: the true answer is $A<B$, so $L$ should be $1$ and $G$ should be $0$. Guess whether $G_{\text{bad}}$ obeys.

Here $A_1=0,A_0=1,B_1=1,B_0=0$.

1. Correct $G$ (guarded). $x_1=\overline{0\oplus 1}=0$. $G=A_1{\bar{B}}_1+x_1{A}_0{\bar{B}}_0=0\cdot 0+0\cdot (1\cdot 1)=0$. Why this step? $x_1=0$ (MSBs differ) correctly muzzles the LSB term. $G=0$ ✔.
2. Correct $L$. $L={\bar{A}}_1{B}_1+x_1{\bar{A}}_0{B}_0=\bar{0}\cdot 1+0=1$. So $L=1$ ✔ ($1<2$).
3. Broken $G_{\text{bad}}$. $G_{\text{bad}}=A_1{\bar{B}}_1+A_0{\bar{B}}_0=0\cdot 0+1\cdot \bar{0}=0+1\cdot 1=1$. Why this step? Without the $x_1$ guard, the LSB term $A_0{\bar{B}}_0=1$ fires even though the MSB already declared $A<B$. Now $G_{\text{bad}}=1$ and $L=1$ simultaneously.

Verify: count of high outputs $G_{\text{bad}}+E+L=1+0+1=2\ne 1$ — the sacred identity is violated (two outputs high at once is impossible). That impossible count is the machine screaming that the guard was dropped. Always guard lower terms with $x_i$.

---

Example 8 — cascaded 7485, local tie passes through (Cell C8)

Forecast: $A=56$, $B=49$, so $A>B$. Guess how the high chip, which sees only equal bits, still reports "greater".

1. Low chip result. Its bits $1000$ vs $0001$: MSB of nibble $1$ vs $0$ → low chip outputs $(A>B)=1,(A=B)=0,(A<B)=0$. Why this step? The low nibble is where the numbers actually differ; it must produce the real decision, exactly like Ex 6.
2. High chip locals. Its bits $0011$ vs $0011$ are all equal → $G_{loc}=0,E_{loc}=1$. Why? $E_{loc}=1$ is the "I couldn't decide, ask the chip below me" flag — the pass-through switch.
3. Cascade wiring. The high chip's $(A>B{)}_{in}$ is wired to the low chip's $(A>B{)}_{out}=1$. Apply the formula (the "$+$" is OR): $(A>B{)}_{out}=G_{loc}+E_{loc}\cdot (A>B{)}_{in}=0+1\cdot 1=1$. Why? Because $E_{loc}=1$ opened the pass-through, the low chip's verdict flows straight to the final output.

Verify: final $A>B=1$; and $56>49$ ✔. This is the human "first-differing-digit" rule scaled up to whole chips.

The figure below draws the two chips as boxes: the orange arrow is the cascade wire carrying the low chip's "$A>B=1$", and the label $E_{loc}=1$ on the high chip marks the open pass-through that lets that verdict flow to the final output.

---

Example 9 — cascaded 7485, local chip decides, cascade blocked (Cell C9)

Forecast: $A=64$, $B=63$. The high nibble already differs. Guess whether the low chip's opinion matters at all.

1. Low chip result. $0000$ vs $1111$: low chip reports $(A<B)$, so the $(A>B{)}_{in}$ handed into the high chip $=0$. Why this step? We deliberately make the low chip say "$A<B$" to test whether the high chip wrongly listens.
2. High chip locals. $0100$ vs $0011$: first differing bit is bit-2 (value 4), where $A=1,B=0$ → $G_{loc}=1$, and $E_{loc}=0$ (bits are not all equal). Why? $E_{loc}=0$ shuts the pass-through gate: it becomes the $0$ multiplier on the cascade term, so nothing from the lower chip can leak through.
3. Cascade formula. $(A>B{)}_{out}=G_{loc}+E_{loc}\cdot (A>B{)}_{in}=1+0\cdot 0=1$. Why? The $E_{loc}=0$ multiplier zeroes the cascade term, so the low chip's contrary "$A<B$" is completely ignored. The high chip decided.

Verify: final $A>B=1$; and $64>63$ ✔ despite the low nibble screaming "less". MSB-nibble authority wins — the same principle as Ex 6, now across chips.

---

Example 10 — word problem: a temperature threshold (Cell C10)

Forecast: $A=11$, threshold $=10$. Guess ON or OFF, then locate which bit triggers it.

4-bit greater (every "$+$" is OR): $G=A_3{\bar{B}}_3+x_3{A}_2{\bar{B}}_2+x_3{x}_2{A}_1{\bar{B}}_1+x_3{x}_2{x}_1{A}_0{\bar{B}}_0$.

Bits: $A=1011$, $B=1010$ (bit 3 is the MSB, bit 0 the LSB).

1. Guards from the top. $x_3=\overline{1\oplus 1}=1$, $x_2=\overline{0\oplus 0}=1$, $x_1=\overline{1\oplus 1}=1$. All three top bits match. Why this step? We scan MSB→LSB; matching bits keep the gates open so the decision slides down to the first differing bit.
2. First difference at LSB. Bit 0: $A_0=1,B_0=0$. The surviving term is $x_3{x}_2{x}_1{A}_0{\bar{B}}_0=1\cdot 1\cdot 1\cdot (1\cdot 1)=1$. All higher terms are $0$ because $A_i{\bar{B}}_i=0$ where bits matched. Why? Only the lowest bit differs, and there $A>B$, so the fully-guarded LSB term is the one that fires.
3. Result. $G=0+0+0+1=1$ → fan ON.

Verify: $G=1$; and $11>10$ ✔. A single-bit difference at the very bottom, correctly propagated by three open guards, drives the real-world actuator. This is why the $x_i$ chain is not optional decoration — it is the whole comparison machine. (An alternate route: compute $A-B$ and check the sign — see Binary Subtraction.)

---

Recall

Recall Quick self-test on the scenarios

When MSBs differ, do lower-bit terms ever fire? ::: No — the guard $x_{n-1}=0$ kills them all. In Ex 6, why doesn't counting 1s work? ::: Magnitude is set by the highest differing bit, not the count of 1s. What impossible count reveals a dropped guard? ::: two outputs high at once, so $G+E+L$ counts to $2$. In a cascaded 7485, what makes the cascade input ignored? ::: $E_{loc}=0$ zeroes the pass-through term. What flag opens the pass-through to the lower chip? ::: $E_{loc}=1$ (local bits all equal). Does the "bigger pattern wins" rule hold for signed numbers? ::: No — these comparators are unsigned; signed compare treats the MSB as a sign bit.

---

Connections

• Comparators — parent note with the base equations
• XOR and XNOR Gates — the guard $x_i$ is XNOR
• Truth Tables and Minterms — reading $G,E,L$ off rows (Ex 1)
• Binary Subtraction — alternate compare via sign of $A-B$; also the signed-compare route (Ex 10)
• Multiplexers — another decision block
• Ripple Carry Adder — contrast: LSB-first vs comparator MSB-first (Ex 6)
• 7485 IC — the cascadable chip (Ex 8–9)