MOSFET as a switch: Worked examples — Hardware deep dive

Before we start, let us re-anchor the symbols so no term is used before it is earned:

Definition Every symbol we will lean on

$V_{GS}$ = gate-to-source voltage = (voltage at the Gate pin) minus (voltage at the Source pin). It is the "how hard am I squeezing the valve" number. Picture two probe tips: red on Gate, black on Source; the meter reads $V_{GS}$ .
$V_{D S}$ = drain-to-source voltage = (voltage at the Drain pin) minus (voltage at the Source pin). It is the voltage the closed switch drops while carrying current.
$V_{T H}$ = threshold voltage = the smallest $V_{GS}$ that first opens a conducting path. See Threshold voltage VTH.
$R_{D S (o n)}$ = the leftover resistance of the fully-closed switch, in ohms. Not zero — a real resistor. See R_DS(on) and switching losses.
$V_{D D}$ = the supply rail voltage — the "top of the circuit," the highest voltage the battery/power supply provides.
$R_{L}$ = the load resistance — the thing you are switching power into (a heater, an LED string modelled as a resistor, etc.), sitting in series with the switch.

The one master formula we reuse everywhere (derived in the parent, small- $V_{D S}$ triode approximation):

The scenario matrix

A MOSFET-switch problem can only fall into a handful of "shapes." Here is the full list. Every worked example below is tagged with the cell(s) it covers, so you can see the grid fill up.

Cell	Scenario class	The thing being tested
A	$V_{GS} < V_{T H}$	OFF / cut-off case
B	$V_{GS} = V_{T H}$ exactly	the degenerate boundary (overdrive $= 0$ )
C	$V_{GS} ≫ V_{T H}$ , $V_{D S}$ small	fully-ON, deep triode (ohmic)
D	Overdrive → large	limiting behaviour of $R_{D S (o n)}$
E	Load-line / $V_{o u t}$	low-side inverter output, both states
F	Power & heat	$P_{co n d}$ , thermal sanity
G	Real-world word problem	LED driver sizing
H	Exam twist: high-side	why gate-at- $V_{D D}$ fails; the sign trap
I	P-channel sign flip	negative $V_{GS}$ , opposite logic
J	$V_{D S} ≳ V_{GS} - V_{T H}$	saturation edge — formula breaks
K	$V_{D S} < 0$ (reverse)	body-diode conduction quadrant

Cells A, B, C, D are the behaviour-vs-overdrive axis. E, F are the circuit-consequence axis. G, H, I are the traps. J, K are the edge quadrants most notes forget. We cover all eleven.

Figure 1 below draws the overdrive axis (Cells A–D) so you can see where OFF, boundary and fully-ON live.

Worked examples

Example 1 — Cell A: below threshold (OFF)

Worked example Statement

$V_{T H} = 2.5 V$ . The gate driver can only reach $V_{GS} = 2.0 V$ . Is the switch ON or OFF, and what is $R_{D S (o n)}$ ?

Forecast: Guess before reading — is $2.0$ enough?

Compute overdrive $V_{GS} - V_{T H} = 2.0 - 2.5 = - 0.5 V$ . Why this step? The overdrive's sign is the whole answer: negative means we never reached threshold.
Interpret. Negative overdrive ⇒ no inversion layer ⇒ cut-off. The channel does not exist. Why this step? Plugging a negative overdrive into $R_{D S (o n)} = 1/ [k (V_{GS} - V_{T H})]$ would give a negative resistance — a nonsense number, which is the formula screaming "I am out of my valid region." The triode formula only applies once the channel exists.
State the physical resistance: $R_{D S (o n)} \to \infty$ (an open switch). Switch is OPEN.

Verify: In a low-side circuit with $R_{L}$ , an open switch means no current, so $V_{o u t} \approx V_{D D}$ — the HIGH state, which is exactly what "switch open, load un-pulled-down" should give. Consistent.

Example 2 — Cell B: exactly at threshold (the degenerate input)

Worked example Statement

$V_{T H} = 2.5 V$ , driven to exactly $V_{GS} = 2.5 V$ , with $k = 3 A/V^{2}$ . What does $R_{D S (o n)}$ evaluate to?

Forecast: What happens when you divide by an overdrive of zero?

Overdrive $= 2.5 - 2.5 = 0$ . Why this step? This is the knife-edge case the matrix demands we not skip.
Substitute: $R_{D S (o n)} = \frac{1}{3 \times 0} = \frac{1}{0}$ → undefined / infinite. Why this step? The math is telling us that right at threshold the channel is just barely forming — infinitely faint, infinitely resistive. There is no useful conduction here.
Conclusion: exactly $V_{GS} = V_{T H}$ is not a usable ON state. It is the boundary, belonging to neither a good OFF nor a good ON.

Verify: As overdrive shrinks toward $0^{+}$ , $R_{D S (o n)} = 1/ (k \cdot overdrive) \to \infty$ . The limit agrees with the substitution. This is why the third parent-note mistake ("just barely exceed $V_{T H}$ ") is fatal — you sit next to a resistance blow-up.

Example 3 — Cell C + Cell D: fully ON, and the limiting trend

Worked example Statement

$k = 2 A/V^{2}$ , $V_{T H} = 2 V$ , and we keep $V_{D S}$ small (deep triode). Tabulate $R_{D S (o n)}$ at $V_{GS} = 3, 5, 10, 20 V$ . What does $R_{D S (o n)}$ approach as $V_{GS} \to \infty$ ?

Forecast: Does doubling the drive halve the resistance? Does it ever hit zero?

Overdrives: $1, 3, 8, 18 V$ . Why this step? $R_{D S (o n)}$ depends only on overdrive, never on $V_{GS}$ alone.
Apply $R_{D S (o n)} = 1/ (k \cdot overdrive) = 1/ (2 \cdot overdrive)$ :
- $V_{GS} = 3$ : $1/ (2 \cdot 1) = 0.5 Ω$
- $V_{GS} = 5$ : $1/ (2 \cdot 3) = 0.1667 Ω$
- $V_{GS} = 10$ : $1/ (2 \cdot 8) = 0.0625 Ω$
- $V_{GS} = 20$ : $1/ (2 \cdot 18) = 0.02778 Ω$ Why this step? Each row is one point on the curve of Figure 2 — resistance falling as we squeeze harder. (Valid because we specified $V_{D S}$ small, keeping us in the ohmic zone.)
Limit: as overdrive $\to \infty$ , $R_{D S (o n)} = 1/ (k \cdot \infty) \to 0^{+}$ . Why this step? Cell D asks for limiting behaviour. Ideal-model resistance decays to zero but never reaches it — a hyperbola $1/ x$ , never touching the axis. (Real devices flatten out due to fixed metal/contact resistance, but the model says "keep improving with diminishing returns.")

Verify: From $V_{GS} = 10$ to $20$ , overdrive went $8 \to 18$ (ratio $2.25 \times$ ), so $R_{D S (o n)}$ should fall by $2.25 \times$ : $0.0625/2.25 = 0.02778 Ω$ . ✓ matches the table.

Figure 2 plots this table: the smooth $1/ x$ -shaped curve with the four orange dots is your visual proof that harder gate drive buys ever-less resistance, and that the curve hugs — but never touches — zero.

Example 4 — Cell E: low-side output in BOTH states

Worked example Statement

Low-side switch: $V_{D D} = 5 V$ , load $R_{L} = 220 Ω$ . ON-resistance $R_{D S (o n)} = 0.08 Ω$ . Find $V_{o u t}$ when ON and when OFF, and confirm it inverts the logic.

Forecast: How close to 0 V does ON get? Exactly 0?

ON state — the drain node is the divider output: $V_{o u t} = V_{D D} \frac{R _{D S (o n)}}{R _{D S (o n)} + R _{L}} = 5 \cdot \frac{0.08}{0.08 + 220}$ Why this step? The closed switch $R_{D S (o n)}$ and the load $R_{L}$ form a series voltage divider from $V_{D D}$ to ground; the output is read at their junction. (Here $V_{D S} = V_{o u t} \approx 1.8 mV$ is tiny, so the ohmic-region $R_{D S (o n)}$ is legitimately valid.)
Evaluate: $5 \times 0.08/220.08 = 5 \times 3.635 \times 1 0^{- 4} = 1.818 \times 1 0^{- 3} V \approx 1.82 mV$ ≈ LOW. Why this step? Because $R_{D S (o n)} ≪ R_{L}$ , almost all $V_{D D}$ drops across $R_{L}$ , leaving a whisker across the switch. Not exactly 0 — that whisker is the price of finite $R_{D S (o n)}$ .
OFF state: $R_{D S (o n)} \to \infty$ , so $V_{o u t} = V_{D D} \cdot \frac{\infty}{\infty + 220} \to V_{D D} = 5 V =$ HIGH. Why this step? Open switch = no current = no drop across $R_{L}$ , so the drain sits at the top rail.

Verify: Input HIGH (gate driven, ON) → output LOW; input LOW (gate off) → output HIGH. That is exactly a logic inverter — consistent with Logic gates from MOSFETs (CMOS). Numerically $1.82 mV$ vs $5 V$ : a clean $0$ / $1$ separation. ✓

Example 5 — Cell F: conduction power and a thermal sanity check

Worked example Statement

A MOSFET carries $I_{D} = 4 A$ with $R_{D S (o n)} = 0.05 Ω$ . Its thermal resistance to ambient is $θ_{J A} = 40^{\circ} C/W$ and ambient is $25^{\circ} C$ . Find the conduction loss and the junction temperature. Is it safe (limit $150^{\circ} C$ )?

Forecast: Will $4 A$ through $50 m Ω$ cook it?

Power: $P_{co n d} = I_{D}^{2} R_{D S (o n)} = 4^{2} \times 0.05 = 16 \times 0.05 = 0.8 W$ . Why this step? Joule heating — the fundamental heat source of a closed switch.
Temperature rise: $Δ T = P \cdot θ_{J A} = 0.8 \times 40 = 32^{\circ} C$ . Why this step? Thermal resistance ( $^{\circ}$ C per watt) times watts gives the rise, exactly like a voltage divider but for heat.
Junction temp: $T_{J} = 25 + 32 = 57^{\circ} C$ . Why this step? Add the rise to ambient. $57 < 150$ ⇒ safe, no heatsink needed.

Verify: Units: $A^{2} \cdot Ω = A^{2} \cdot (V/A) = A \cdot V = W$ ✓. If $R_{D S (o n)}$ were $10 \times$ larger ( $0.5 Ω$ ), $P = 8 W$ , $Δ T = 320^{\circ} C$ , $T_{J} = 345^{\circ} C$ — destroyed. This is exactly why datasheets fixate on $R_{D S (o n)}$ . ✓

Example 6 — Cell G: real-world word problem (LED strip driver)

Worked example Statement

You switch a $12 V$ LED strip drawing $2.5 A$ with a low-side N-MOSFET. Your gate driver gives $V_{GS} = 10 V$ ; the device has $k = 1.5 A/V^{2}$ , $V_{T H} = 1.8 V$ . Find $R_{D S (o n)}$ , the voltage lost across the MOSFET, and the conduction loss.

Forecast: How many millivolts does the switch steal from the LEDs?

Overdrive $= 10 - 1.8 = 8.2 V$ (deep triode — a good switch). Why this step? Confirms we are in the fully-ON regime the formula assumes.
$R_{D S (o n)} = 1/ (k \cdot overdrive) = 1/ (1.5 \times 8.2) = 1/12.3 = 0.08130 Ω$ . Why this step? Turns the drive level into an actual resistance.
Voltage across MOSFET: $V_{D S} = I_{D} R_{D S (o n)} = 2.5 \times 0.08130 = 0.2033 V$ . Why this step? This is how much of the $12 V$ the strip doesn't get. Only $\sim 0.2 V$ — negligible for LEDs. Note $V_{D S} = 0.2 V ≪ 8.2 V$ overdrive, so the ohmic-region formula is valid here.
Power: $P_{co n d} = I_{D}^{2} R_{D S (o n)} = 2. 5^{2} \times 0.08130 = 6.25 \times 0.08130 = 0.5081 W$ . Why this step? Design deliverable: half a watt is easy to dissipate in a small TO-220.

Verify: Cross-check $P$ two ways — $I_{D}^{2} R = 0.5081 W$ and $V_{D S} \cdot I_{D} = 0.2033 \times 2.5 = 0.5081 W$ . Both routes agree. ✓

Example 7 — Cell H: the high-side trap (exam twist)

Worked example Statement

An N-channel MOSFET is placed on the high side: drain to $V_{D D} = 12 V$ , source to the load (load's other end to ground), $V_{T H} = 2 V$ . A beginner ties the gate to $V_{D D} = 12 V$ expecting "fully on." When the switch tries to conduct, the source rises to $11 V$ . What is the actual $V_{GS}$ , and is it ON?

Forecast: Gate is at the highest rail — surely that's max ON?

Definition first: $V_{GS} = V_{G} - V_{S}$ , not $V_{G}$ alone. Why this step? This is the entire trap — people read $V_{G} = 12$ and stop.
Substitute the risen source: $V_{GS} = 12 - 11 = 1 V$ . Why this step? As the N-channel conducts, current flows into the load and the source floats up toward $V_{D D}$ ; the gate can't stay ahead of it.
Compare to threshold: $1 V < 2 V = V_{T H}$ ⇒ overdrive $= - 1 V$ ⇒ it turns itself OFF. A self-defeating loop: try to turn on → source rises → $V_{GS}$ collapses → off. Why this step? Shows the failure is a moving-reference problem, echoing the parent note's fourth mistake.
The fix: to keep overdrive positive you need $V_{G} > V_{D D} + V_{T H} = 12 + 2 = 14 V$ — a bootstrap/charge pump, or use a P-channel device. See Low-side vs High-side switching.

Verify: For a proper $3 V$ overdrive with source at $\sim 12 V$ , you'd need $V_{G} = 12 + 2 + 3 = 17 V$ , indeed above $V_{D D}$ . The low-side topology of Examples 4–6 avoids all this because the source is pinned to ground, so $V_{GS} = V_{G}$ . ✓

Example 8 — Cell I: the P-channel sign flip

Worked example Statement

A P-channel MOSFET has $V_{T H} = - 2 V$ (thresholds are negative for P-channel). Its source sits at $V_{D D} = 5 V$ ; you drive the gate to $V_{G} = 0.5 V$ . Is it ON? Then find $R_{D S (o n)}$ given $k_{p} = 1 A/V^{2}$ (using $∣ V_{GS} - V_{T H} ∣$ ).

Forecast: For a P-channel, does lower gate voltage turn it ON?

$V_{GS} = V_{G} - V_{S} = 0.5 - 5 = - 4.5 V$ . Why this step? P-channel sources sit at the top, so $V_{GS}$ is naturally negative — the opposite sign world from N-channel.
Turn-on test: a P-channel is ON when $V_{GS} < V_{T H}$ (more negative than threshold). Here $- 4.5 < - 2$ ⇒ ON. Why this step? The inequality flips because everything about P-channel is mirror-imaged; see Enhancement vs Depletion MOSFET.
Overdrive magnitude: $∣ V_{GS} - V_{T H} ∣ = ∣ - 4.5 - (- 2) ∣ = ∣ - 2.5∣ = 2.5 V$ . Why this step? The resistance formula uses the magnitude of overdrive, so signs cancel cleanly.
$R_{D S (o n)} = 1/ (k_{p} \cdot 2.5) = 1/ (1 \times 2.5) = 0.4 Ω$ .

Verify: Sanity: pulling the gate toward ground (below $V_{D D}$ ) makes $V_{GS}$ more negative and turns a P-channel ON — the exact mirror of an N-channel needing gate above source. That mirror pairing is what makes a CMOS inverter work: N pulls low, P pulls high. ✓

Example 9 — Cell J: when $V_{D S}$ is NOT small (the saturation edge)

Worked example Statement

N-MOSFET, $V_{GS} = 5 V$ , $V_{T H} = 2 V$ (overdrive $= 3 V$ ), $k = 2 A/V^{2}$ . The circuit forces $V_{D S} = 4 V$ across it. May we use $R_{D S (o n)} = 1/ [k (V_{GS} - V_{T H})]$ ? What is the drain current really?

Forecast: Is $4 V$ "small" compared to a $3 V$ overdrive?

Check the domain first: the ohmic formula needs $V_{D S} ≪ V_{GS} - V_{T H} = 3 V$ . Here $V_{D S} = 4 V > 3 V$ . The condition is violated. Why this step? This is the whole point of Cell J: blindly applying $R_{D S (o n)}$ here is the classic error the domain warning guards against.
Identify the region: a MOSFET is in saturation when $V_{D S} \geq V_{GS} - V_{T H}$ . Since $4 \geq 3$ , we are in saturation, not the resistor-like triode — so there is no fixed $R_{D S (o n)}$ to speak of. Why this step? In saturation the device behaves like a constant-current source, not a resistor; see Triode vs Saturation regions.
Use the saturation current instead: $I_{D} = \frac{k}{2} (V_{GS} - V_{T H})^{2} = \frac{2}{2} (3)^{2} = 9 A$ , essentially independent of $V_{D S}$ . Why this step? This is the correct model in this region; the current is set by overdrive, not by $V_{D S} / R$ .

Verify: If we had wrongly used the ohmic formula, $R_{D S (o n)} = 1/ (2 \cdot 3) = 0.1667 Ω$ would predict $I_{D} = V_{D S} / R = 4/0.1667 = 24 A$ — nearly $3 \times$ the true $9 A$ . The huge disagreement confirms the ohmic formula must not be used once $V_{D S} \geq$ overdrive. For a good switch you keep $V_{D S}$ tiny precisely to stay in triode and avoid this. ✓

Example 10 — Cell K: reverse current and the body diode

Worked example Statement

An N-MOSFET switch is OFF ( $V_{GS} = 0$ ), but the load is inductive (a motor coil) and tries to push $2 A$ backward through the device, forcing the source $0.7 V$ above the drain (so $V_{D S} = - 0.7 V$ ). What conducts, and how much power does it burn?

Forecast: If the channel is OFF, can any current flow at all?

Recall the hidden diode: every N-MOSFET has an intrinsic body diode from source (anode) to drain (cathode), formed by the body-drain PN junction. Why this step? This diode is the reason "OFF" is not a perfect open circuit for reverse current — a quadrant most notes ignore.
Check its orientation: current pushed from source→drain is forward for this diode. With $V_{D S} = - 0.7 V$ (source higher), the diode is forward-biased and conducts, even though the channel is off. Why this step? Sign of $V_{D S}$ decides whether the body diode turns on; a negative $V_{D S}$ of about one diode drop ( $\approx 0.7 V$ ) means it is conducting.
Power in the diode: $P = V_{f} \cdot I = 0.7 \times 2 = 1.4 W$ dissipated in the body diode. Why this step? Unlike $R_{D S (o n)}$ (which scales as $I^{2} R$ ), the diode drop is roughly fixed at $\sim 0.7 V$ , so loss scales as $V_{f} \cdot I$ — often worse at high current. This is why synchronous rectifiers turn the channel on to shunt the body diode.

Verify: Two regimes for a MOSFET carrying reverse current: (a) channel OFF → body diode, loss $= 0.7 \times 2 = 1.4 W$ ; (b) channel ON with $R_{D S (o n)} = 0.05 Ω$ → loss $= I^{2} R = 2^{2} \times 0.05 = 0.2 W$ . Turning the channel on cuts loss $7 \times$ — the exact motivation for synchronous switching. Both numbers positive, units in watts. ✓

Recall

Recall Cover the answers — one per matrix cell

Cell A ( $V_{GS} < V_{T H}$ ): what is $R_{D S (o n)}$ ? ::: infinite (open switch, cut-off)
Cell B ( $V_{GS} = V_{T H}$ ): why is this unusable? ::: overdrive $= 0$ , so $R_{D S (o n)} = 1/0 = \infty$
Cell D (limit $V_{GS} \to \infty$ ): what does $R_{D S (o n)}$ approach? ::: $0^{+}$ , but never exactly zero
Cell E (OFF, low-side): what is $V_{o u t}$ ? ::: $\approx V_{D D}$ (HIGH)
Cell F: formula for conduction loss? ::: $P = I_{D}^{2} R_{D S (o n)}$
Cell H: why does gate-at- $V_{D D}$ fail high-side? ::: source floats to $\approx V_{D D}$ , so $V_{GS} \to 0 < V_{T H}$
Cell I: a P-channel is ON when? ::: $V_{GS} < V_{T H}$ (both negative), gate pulled below source
Cell J: when is the ohmic $R_{D S (o n)}$ formula invalid? ::: when $V_{D S} \geq V_{GS} - V_{T H}$ (device in saturation)
Cell K: what conducts when the OFF MOSFET sees reverse current? ::: the intrinsic body diode ( $\approx 0.7 V$ drop)

Connections

2.4.14 MOSFET as a switch (parent)
Triode vs Saturation regions
Threshold voltage VTH
R_DS(on) and switching losses
Low-side vs High-side switching
Enhancement vs Depletion MOSFET
Logic gates from MOSFETs (CMOS)
BJT as a switch