5.5.22 · D4 · HinglishEmbedded Systems & Real-Time Software

ExercisesSoftware-in-the-Loop (SIL) simulation — all software, simulated hardware

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5.5.22 · D4 · Coding › Embedded Systems & Real-Time Software › Software-in-the-Loop (SIL) simulation — all software, simula


Level 1 — Recognition

L1.1 — "In the loop" kya hai?

Recall Solution

Answer: (b). "Loop" ek closed-loop feedback path hai. Neeche figure dekho: do boxes hain — left mein Software (SUT) aur right mein Plant model. Red arrow follow karo — yeh woh command hai jo software bahar bhejta hai. Phir black arrow wapas follow karo — yeh woh sensor value hai jo plant return karta hai, jo software ka next input ban jaata hai. Kyunki output loop hokar next input ban jaata hai, data-flow ek closed circle form karta hai — woh circle hi "loop" hai, code mein koi for-loop nahi.

Figure — Software-in-the-Loop (SIL) simulation — all software, simulated hardware

Figure L1.1: closed SIL feedback loop. Red = command signal (key object); black = returned sensor signal jo cycle band karta hai.

(a) ek distractor hai: kisi bhi program mein for loops hote hain. (c) developer ke workflow ko describe karta hai, runtime signal path ko nahi.

L1.2 — Component match karo

Recall Solution

1→B, 2→C, 3→A, 4→D.

  • SUT (1→B): woh real code jo tum ship karoge.
  • Plant model (2→C): equations jo motors/sensors ko replace karti hain.
  • Cosim framework (3→A): woh orchestrator jo dono clocks ko step karta hai.
  • HAL (4→D): Hardware Abstraction Layer — woh seam jo same core logic ko PC (SIL) ya MCU (production) dono par sirf yeh layer swap karke run karti hai.

L1.3 — Kaun sa stage kaun sa bug pakadta hai?

Recall Solution

Nahi. Ek linear model mein koi saturation limit nahi hoti, isliye actuator command kabhi clamp nahi hoti — windup condition (command max par pinned rehna jab error integrate hota rahe) kabhi occur hi nahi hoti. Tumhe ek high-fidelity model chahiye jisme if speed > max_rpm: speed = max_rpm jaisi limit ho.


Level 2 — Application

L2.1 — Haath se ek Euler tick

Recall Solution

Kya karein: current state par derivative evaluate karo, phir aage step karo. Euler kyun aur kuch fancy kyun nahi? Euler sabse sasta solver hai — ek derivative evaluation per step. Pehli nazar ke liye theek hai; iska cost accuracy hai, jo L3 mein address hoti hai.

L2.2 — Do ticks, state carry dekho

Recall Solution

Derivative dobara evaluate kyun karein? "In-the-loop" ka poora point yahi hai ki naya state next step ko feed karta hai. Dhyan do increment chhota ho gaya (): model apni steady value ki taraf approach kar raha hai. Woh steady value ki taraf lag exactly woh dynamic behaviour hai jo ek medium-fidelity model (upar box mein define kiya gaya — first-order rule) reveal karne ke liye exist karta hai, aur jo low-fidelity speed = K*u model bilkul miss kar deta.

L2.3 — Braking scenario

Recall Solution

Units pehle kyun convert karein? Model ke terms metres aur seconds (SI) mein hain. km/h ko ek formula mein mix karna jo m/s expect karta hai, physics ko silently galat scale kar dega — ek classic SIL unit bug jo low-fidelity check pakadne ke liye exist karta hai. Conversion factor: aur , isliye Isliye . Yeh ek repeating decimal hai; hum exact fraction arithmetic mein carry karte hain aur final answers ko sirf end mein 3 decimals par round karte hain (writing ya ek exact fraction ka rounded display hai, kabhi woh value nahi jo hum wapas feed karein).

Deceleration . Distance update purani velocity se kyun? Yeh Euler ka rule hai — woh interval ke start par state use karta hai. (Agar tumne ko pehle par round kiya aur wapas feed kiya, tum aur padhte — danger display digits mein nahi, balki next computation se pehle rounding mein hai.)


Level 3 — Analysis

L3.1 — Bada blow up kyun karta hai?

Recall Solution

Per-step multiplier hai; har step ko se multiply karta hai. Figure mein red curve woh hai jo diverge hoti hai — woh case hai jisse darna chahiye.

Figure — Software-in-the-Loop (SIL) simulation — all software, simulated hardware

Figure L3.1: same decaying state ke teen Euler runs. X-axis = simulated time (s); Y-axis = state . Black solid = stable decay; black dashed = oscillating-but-shrinking; red = diverging. Dekho kaise sirf red run zero se door magnitude mein grow karta hai.

ke har range ko, boundaries including, walk karte hain:

  • Degenerate boundary (): koi step nahi liya jaata, isliye kabhi change nahi hoti — state frozen hai. Yeh trivially "stable" hai par useless: zero time advance ke saath simulation koi progress nahi karta. Hum ise completeness ke liye list karte hain, kyunki yeh woh exact edge hai jahan step size vanish hoti hai.
  • (): smooth monotone decay toward 0 — correct physics (black solid).
  • Boundary (): state ek single step mein exactly 0 par snap ho jaati hai aur wahan rehti hai. Harmless par non-physical (real decay gradual hai, kabhi instant nahi).
  • (): har step sign flip hota hai par magnitude shrink hoti hai — ek decaying oscillation (black dashed). Non-physical wobble, par blow up nahi karta.
  • Boundary (): marginal stability forever flip karta hai constant magnitude par, kabhi settle nahi karta. Yeh stable aur unstable ke beech ka knife-edge hai.
  • (): har step magnitude grow karta hai — true divergence (red curve). Yahi woh "numerical instability" hai jiske baare mein parent note warn karta hai.

SIL ke liye yeh kyun important hai: "faster run karne ke liye" bahut bada choose karna plant model ko aisi physics report karwa sakta hai jo kabhi hoti hi nahi, toh tum ek simulation artifact debug karoge, apna code nahi.

L3.2 — Fidelity budget padhna

Recall Solution

6% abstraction error kahan se aata hai? (WHY, derived, asserted nahi): ADC (analog-to-digital converter) ko ek conversion finish karne ke liye 2 clock cycles chahiye; 1 kHz control rate par control period hai... lekin yahan delay ek loop period ke relative quote kiya gaya hai, giving ek fractional delay of a cycle. cycles ka ek pure time delay, first order par, loop se phase margin remove karne ke barabar hai: yeh ek phase angle subtract karta hai loop ke crossover par phase margin ka (yahan crossover sample rate ke ek-sathven ke paas baithta hai, ek typical well-tuned value). Ab standard second-order overshoot-vs-phase-margin relation use karo — textbook approximation ki overshoot percentage nominal margin ke paas, yaani phase margin lose karna overshoot roughly one-for-one band mein add karta hai. margin lose karna isliye order of extra overshoot add karta hai. Toh "" ek derived engineering estimate known 2-cycle delay se hai, koi chart se nahi nikala — aur critically, SIL kabhi yeh delay model nahi karta, isliye woh yeh term dekh hi nahi sakta.

Worst-case bound: possible prediction error — margin se bada, isliye SIL akela is spec ke liye trustworthy nahi hai. Pehle kaun sa term? Abstraction error (6%) dominant hai aur woh hai jo SIL structurally dekh hi nahi sakta. Yeh ek unmodeled effect hai (ADC conversion delay), isliye koi bhi solver tuning ise fix nahi kar sakta. Yahi "necessary-but-not-sufficient" limit hai: is spec ki check PIL/HIL par le jaao jahan real timing appear hoti hai, aur discretization sirf tab shrink karo jab woh sasta ho.


Level 4 — Synthesis

L4.1 — HAL cut kahan hai?

Recall Solution

Pehle, samjho har symbol ka matlab kya hai: pid(error) ek pure-computation controller hai — input tracking error hai, output command hai; koi hardware nahi touch karta, isliye yeh core logic hai aur wahi rehta hai. Offending line instead woh direct memory-mapped register read *(volatile int*)0x4001A004 hai. Yeh hardware-specific hai aur host PC par exist nahi kar sakti. Refactor — ise HAL call ke peeche le jaao:

int hal_read_sensor(void);   // SIL: plant-model value return karta hai
                             // MCU: 0x4001A004 read karta hai
int control_step(void) {
    int raw = hal_read_sensor();       // core logic untouched
    int cmd = pid(setpoint - raw);     // pid() unchanged, still pure
    return cmd;
}

Ab control_step platform-independent hai: . SIL mein framework ek hal_read_sensor link karta hai jo plant model ki sensor value return karta hai; target par woh register version link karta hai. Yeh Unit Testing for Embedded Systems se mirror karta hai, jahan same seam tumhe stub inputs inject karne deta hai.

L4.2 — Ek two-stage plan design karo

Recall Solution
  • (i) Sign error → SIL. Yeh pure algorithm logic hai. Plant model se ek known rotating input feed karo; ek sign flip fused angle ko immediately ground truth se diverge kar deta hai, sasta, software mein.
  • (ii) EMI-spike crash → HIL. EMI outlier ek abstraction-error effect hai — real electrical noise with heavy-tailed spikes jo ek clean Gaussian SIL model produce nahi karega. Real analog front-end + wiring (HIL) woh jagah hai jahan aisi glitches actually appear hoti hain. Plan: SIL pehle (sasta logic bug pakdo), phir HIL (physical-world bug pakdo). Yeh parent note ka "necessary but not sufficient" doctrine applied hai.

Level 5 — Mastery

L5.1 — Euler vs RK4 cost/accuracy trade-off

Recall Solution

Yeh thresholds kyun (WHY): local error per step scale hoti hai ki tarah, jahan method ka order hai — Euler order hai, RK4 order hai. Same small error target hit karne ke liye:

  • Euler: error , isliye — ek loose bound, bahut se chhote steps force karta hai; "" capture karta hai ek time constant resolve karne ke liye 10 steps ki zaroorat.
  • RK4: error , jo dramatically faster shrink hoti hai, isliye same bahut bade step se meet hoti hai — "" (approximately 2 steps per time constant).

Allowed step sizes ka ratio RK4 ke higher order ka payoff hai. Ab counting:

Euler: → steps → evals . RK4: → steps → evals . Decision: RK4 yahan sasta hai — 48000 < 60000 evals — aur zyada accurate bhi, kyunki uska bada stable step uski 4× per-step cost se zyada hai. Lesson: "Euler fast hai" ek per-step claim hai; total cost = steps × cost/step, aur ek stiffer accuracy demand winner flip kar sakti hai.

L5.2 — Kya SIL yahan sufficient hai? Judgment call

Recall Solution

Argument: SIL ki prediction error (model + discretization + abstraction) error se bounded hai, aur abstraction term exactly un effects ko cover karta hai jo tumne model nahi kiye — sensor EMI spikes, MCU timing jitter, voltage sag — isliye 100000 passing scenarios sirf tumhare model ke duniya mein correctness prove karte hain, bahar nahi. Zero SIL failures un-modeled term ko bound nahi kar sakte. Sahi move: SIL algorithm correctness prove karta hai; Hardware-in-the-Loop (HIL) aur ek Real-Time Operating Systems (RTOS)-scheduled real-time run ke through escalate karo timing aur physical robustness validate karne ke liye, kisi bhi ship decision se pehle.


Recall Quick self-test (cloze)

SIL mein, test hone wala artifact software (SUT) hai, jabki plant model ek trusted stand-in hai. Forward Euler har new-state value ko old-state values se compute karta hai. Time constant ke saath decay ke liye, Euler diverge karta hai jab ==, aur exactly par marginally stable hota hai. Woh ek error term jo SIL structurally dekh hi nahi sakta woh hai abstraction error== (unmodeled effects). L2.1 mein ke liye Euler step ::: rad/s L5.1 mein RK4 vs Euler total evals ::: 48000 vs 60000 — RK4 sasta


Parent: Software-in-the-Loop (SIL) simulation — all software, simulated hardware (index 5.5.22) · See also: Hardware-in-the-Loop (HIL) · Unit Testing for Embedded Systems · Real-Time Operating Systems (RTOS) · Sensor Fusion Algorithms