5.5.15 · D3Embedded Systems & Real-Time Software

Worked examples — Bare-metal vs RTOS — when to use each

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Before we start, every symbol used below is earned. If any is unfamiliar, here is the plain-words dictionary — nothing on this page uses a symbol not on this list.


The scenario matrix

Every scheduling problem in this topic is one of these case classes. Each row is a "cell" you must be able to handle. The right column names the worked example that covers it.

# Case class What makes it special Covered by
A Super-loop, everything fits every deadline → bare-metal wins Ex 1
B Super-loop, one slow job breaks it Fast critical job misses deadline → need RTOS Ex 2
C RM utilisation test PASSES → guaranteed schedulable Ex 3
D Utilisation between bound and 1 Test fails but system may still be OK → exact RTA needed Ex 4
E Full response-time iteration Show the recurrence converging step by step Ex 5
F Degenerate: / single task Zero-work or one-job limits Ex 6
G Limiting case: and Bound ; what "100% full" means Ex 7
H Equal periods (tie-break) Two tasks share a period → who goes first? Ex 8
I Real-world word problem Translate an English brief into and decide Ex 9
J Exam twist: overload / Provably impossible — must shed load Ex 10

Example 1 — Cell A: super-loop, everything fits

  1. Compute worst-case loop latency. Why this step? In a super-loop every job waits for every other job once per loop, so the killer number is .
  2. Compare to the tightest deadline. Why this step? A design is safe only if the worst wait is smaller than the shortest deadline. The tightest deadline here is the pressure job's period, ms.
  3. Decide. Why this step? If the loop already meets every deadline with 12× slack, an RTOS only adds RAM and complexity for no timing benefit.

Example 2 — Cell B: one slow job breaks the loop

  1. Super-loop latency for the control loop. Why this step? In one loop the control job must wait behind the SD write once.
  2. Compare to deadline. Why this step? The control deadline is ms.
  3. Fix with pre-emption. Why this step? Under an RTOS make the control task highest priority. Its response time (defined in the vocabulary above — the time from ready to finished, including interruptions) now has no higher-priority interrupters, so and the summation is empty:

Example 3 — Cell C: the RM utilisation test passes

  1. Total utilisation. Why this step? is the fraction of CPU demanded; it's the cheapest test to try first.
  2. Liu & Layland bound for . Why this step? Rate-Monotonic guarantees deadlines if is below — a sufficient (safe-if-passed) test. See Rate-Monotonic Scheduling.
  3. Compare. Why this step? If bound, we are done — no need for the harder response-time analysis.

Example 4 — Cell D: utilisation between the bound and 1

  1. Utilisation. Why this step? Try the cheap test first, .
  2. Bound. Why this step? Compare to for . The utilisation sits between the bound and full loading — the true grey zone.
  3. Fall back to exact response-time analysis. Why this step? A failed utilisation test means "don't know", not "unschedulable". Run the recurrence on the lowest-priority task (task 3, , pre-empted by and ):
  4. Check the deadline. Why this step? → task 3 meets its deadline despite the failed utilisation test.

Example 5 — Cell E: full response-time iteration

The recurrence from the parent note, is solved by iteration: start with , feed it into the right-hand side to get , repeat until the value stops changing. The figure below shows why it grows in steps and then locks.

Figure — Bare-metal vs RTOS — when to use each
  1. Start. Why this step? The recurrence needs a seed; the smallest possible answer is the task's own work with no interruptions.
  2. Iterate once. Why this step? Over a window of ms, how many times can each higher task pre-empt? arrival of task 1, of task 2.
  3. Iterate again. Why this step? The window grew to 5, so recount arrivals: , .
  4. Iterate again. Why this step? Window is now 6, recount: , .
  5. Stop. Why this step? — the value stopped changing, so we have the fixed point.

Example 6 — Cell F: degenerate inputs (, single task)

  1. (a) Zero-work utilisation. Why this step? . It demands no CPU, adds nothing to any , and its ceiling term . So it is invisible to every deadline.
  2. (b) Single-task utilisation. Why this step? .
  3. Compare. Why this step? For the bound is exactly — a single task can use up to 100% of the CPU and still be trivially schedulable (nothing pre-empts it).

Example 7 — Cell G: the limiting case

The RM bound shrinks as you add tasks. The figure shows it sliding down toward .

Figure — Bare-metal vs RTOS — when to use each
  1. Tabulate. Why this step? Plug into .
  2. Interpret the trend. Why this step? More tasks means their periods are harder to line up, so the guaranteed-safe ceiling drops. You can never guarantee more than ~69.3% loading by this simple rule alone.
  3. Practical reading. Why this step? If your design keeps below , it is RM-schedulable no matter how many tasks you have. That is the safe engineering budget.

Example 8 — Cell H: equal periods (a tie)

  1. Break the tie arbitrarily. Why this step? RM only mandates ordering by period; on a tie any consistent choice is legal. Try ordering 1: A is higher priority.
  2. Response time of the lower task (B) under ordering 1. Why this step? B is pre-empted by A; over B's window exactly one A arrival occurs (they share the period). The higher task keeps its own time: . Both . ✓
  3. Swap the tie — ordering 2: B is higher priority. Why this step? To prove the choice does not decide schedulability, redo it the other way. Now A is the lower task, pre-empted by B once: And . Both . ✓

Example 9 — Cell I: real-world word problem

  1. Translate English into ms. Why this step? Turn each sentence into numbers so the formulas can be applied. IMU , PID , telemetry , SD .
  2. Super-loop test first. Why this step? It is the cheapest way to rule bare-metal in or out. The IMU's worst wait is the whole loop: Bare-metal is fatal — the 25 ms SD write starves the 2 ms IMU.
  3. RTOS utilisation test. Why this step? Check whether an RTOS can even hold the workload, .
  4. Compare to bound and finish with exact RTA. Why this step? For : . Here → utilisation test inconclusive, so run exact response-time analysis on the flight-critical tasks. Give the two 2 ms tasks the top priorities: IMU highest (, nothing above it), PID next (interrupted only by the IMU once in its 2 ms window: ). Both are safely under 2 ms; treat SD/telemetry as best-effort background.

Example 10 — Cell J: exam twist — provable overload

  1. Compute total utilisation. Why this step? is a necessary condition failure — if the tasks demand more than 100% of the CPU, no scheduler can help. This test beats the RM bound as a killer.
  2. Interpret. Why this step? means the workload asks for 160% of one CPU. Deadlines must be missed.
  3. Prescribe the fix. Why this step? An overloaded system has only three cures: lower (faster code / Worst-Case Execution Time (WCET) cuts), raise (run jobs less often), or add hardware (a second core). A watchdog is the safety net if overload ever slips through.

Recall Quick self-check (click to reveal)

Which cell does each fit — "super-loop 16 ms vs 200 ms deadline"? ::: Cell A (everything fits → bare-metal). , bound — pass or fail? ::: Pass (Cell C, guaranteed schedulable). A failed utilisation test means unschedulable — true or false? ::: False — it's inconclusive; run exact RTA (Cell D). What does prove? ::: Provably unschedulable by any algorithm on one CPU (Cell J). Value of the RM bound as ? ::: (Cell G). A task with affects others how? ::: Not at all — zero utilisation, zero response-time contribution (Cell F).


Connections

  • 5.5.15 Bare-metal vs RTOS — when to use each (Hinglish) — parent topic
  • Rate-Monotonic Scheduling — where the utilisation bound and priority ordering come from
  • Worst-Case Execution Time (WCET) — every on this page is a WCET
  • Priority Inversion and Mutexes — the hidden delay term this page's ideal RTA ignores
  • Context Switching — the real cost added each time a higher task pre-empts
  • Watchdog Timers — your safety net when Example 10's overload slips through
  • Interrupts and ISRs — how bare-metal fakes pre-emption without a scheduler