Foundations — Superscalar — multiple execution units

Before you can read the parent note Superscalar, you need to own every symbol it throws at you. This page builds each one from nothing — plain words, a picture, and the reason the topic can't live without it.

0. The clock — the heartbeat everything is measured in

Everything a CPU does is measured in ticks of a clock. Picture a metronome inside the chip going tick… tick… tick… billions of times a second. One "tick" is one clock cycle.

Why the topic needs it: superscalar is about doing more per beat. You cannot count "more per beat" until you have named the beat. Look at the figure below — each vertical white line is one tick.

1. An instruction — the atom of a program

We will write instructions in a simple made-up style:

r1 = r2 + r3

Read this as: "take whatever number is stored in box r2, add the number in box r3, and put the answer in box r1."

Why the topic needs it: the whole game of superscalar is spotting when two instructions touch different boxes (safe to run together) versus the same box (must wait). Registers are the objects we watch.

2. The pipeline — an assembly line for instructions

Before superscalar, understand pipelining (see Pipelining). Building a car, you don't finish one car completely before starting the next — you set up stations (weld, paint, assemble) and a different car sits at each station at once.

A CPU does the same. A classic instruction passes through 5 stages:

1. Fetch — grab the instruction from memory.
2. Decode — figure out what it means.
3. Execute — do the arithmetic.
4. Memory — read/write memory if needed.
5. Write-back — store the result into a register.

Look at the figure: each column is one clock cycle, each row is one instruction. Because the stages overlap, once the pipeline is full, one instruction finishes every cycle — even though each individual instruction still takes 5 cycles start to finish.

3. Execution unit — the workbench that does the actual work

A scalar CPU has essentially one lane through Execute. A superscalar CPU installs several execution units side by side, so several instructions can be in the Execute step in the same cycle.

Look at the two floors in the figure: the top floor (scalar) has one workbench, so instructions queue single-file. The bottom floor (superscalar) has two workbenches, so two independent instructions get built at once.

Why the topic needs it: "multiple execution units" is the definition of superscalar. This is the picture behind the chapter title.

4. Issue width $N$ — how many lanes we built

The symbol $N$ appears constantly in the parent note. Now it just means: count the workbenches.

5. IPC and CPI — the two scorecards

We need a number that says how well we're actually doing. Two mirror-image numbers do this.

Why two names for one idea? Because sometimes it's natural to say "this instruction cost 4 cycles" (CPI language) and sometimes "we finished 2 per cycle" (IPC language). They carry the same information.

6. The performance equation — putting the symbols together

Now we can read the parent note's headline formula. How long does a whole program take?

Read it as a chain of "how many × how much":

• $N_{\text{inst}}$ = how many instructions the program runs (the dynamic count — instructions actually executed, loops counted every pass).
• $\text{CPI}$ = how many cycles each one costs on average.
• $T_{\text{cycle}}$ = how many seconds each cycle lasts.

Multiply them and the cycle-and-instruction units cancel, leaving seconds. Now swap CPI for $1/\text{IPC}$:

$T=\frac{N_{\text{inst}}\times T_{\text{cycle}}}{\text{IPC}}.$

7. Dependency — why the lanes sometimes sit empty

Two instructions are independent if neither needs the other's result. They can run in parallel. If one needs the box the other is still filling, we have a dependency and must wait.

The figure shows two mini-programs. On the left, the arrows never touch — independent, both lanes busy. On the right, each instruction's output feeds the next (a dependency chain) — a single-file line no matter how many lanes exist.

Why the topic needs it: dependencies are the reason real IPC falls short of $N$. This one concept powers the whole "why we rarely hit peak" section of the parent note. Deeper coverage of how the CPU fights dependencies lives in Out-of-Order Execution, Register Renaming, and the Reorder Buffer (ROB) — but the foundation is just: same box → must wait.

8. The parallel fraction $p$ — and Amdahl's shape

The parent note bounds IPC with:

${\text{IPC}}_{\text{eff}}=\frac{1}{(1-p)+\frac{p}{N}}.$

Every symbol is now familiar except $p$.

Test the two extremes — this is exactly Amdahl's Law wearing an ILP costume:

• $p=1$ (everything independent): denominator $=0+\frac{1}{N}=\frac{1}{N}$, so ${\text{IPC}}_{\text{eff}}=N$. Perfect — every lane full.
• $p=0$ (one long dependency chain): denominator $=1+0=1$, so ${\text{IPC}}_{\text{eff}}=1$. Extra lanes are useless.

Prerequisite map

Equipment checklist

Cover the right side and see if you can answer each before revealing.