Foundations — Hazard mitigation — stalling, forwarding - bypassing, branch prediction
This page assumes you have seen nothing. We build every word, every clock, every arrow the parent note leans on, one at a time, each on top of the one before it.
0. The clock — the heartbeat behind everything
Before instructions, before pipelines, there is the clock.
The picture: imagine a metronome. On each click, every worker in a factory takes one step and freezes. Nothing happens between clicks — the world is snapshotted tick by tick.
Why the topic needs it: every diagram in the parent (cyc 1 | 2 | 3 …) is measured in cycles. A "stall" is a wasted tick; "throughput" is answers per tick. Without the clock, none of those words mean anything.
1. What is an "instruction"? What is a register?
The picture: think of registers as 32 numbered cups on the CPU's desk. An instruction like add $t1, $t0, $s1 means: take the number in cup $t0, add the number in cup $s1, drop the result into cup $t1.
Why the topic needs it: the whole forwarding machinery is just comparing "the rd I am about to write" with "the rs/rt someone else wants to read." If you don't know which slot is which, the forwarding formulas are gibberish.
2. lw, add, sub, beq — the four instructions on the parent page
The picture: add/sub are desk work (fast). lw is "walk to the filing cabinet and fetch a folder" (slow, one extra stage). beq is a fork in the road.
Why the topic needs it: the parent's two headline problems are the load-use hazard (born from lw being slow) and the branch penalty (born from beq being a fork). Each traces back to one of these instructions behaving differently from a plain add.
3. The 5 pipeline stages: IF · ID · EX · MEM · WB
The picture — the assembly line: five workers in a row. At any tick, 5 different instructions occupy the 5 stages. See the figure: the diagonal shows each instruction sliding one stage rightward per cycle.
Why the topic needs it: hazards happen because instruction A is still in (say) MEM while instruction B has reached EX and wants A's answer. You cannot see that collision without the staircase picture of overlapping stages.
Recall Why does overlap create throughput?
Without overlap, one instruction finishes before the next starts (5 cycles each). With overlap, once the line is full, one instruction completes every cycle ::: because all 5 workers are busy on 5 different instructions at once.
4. The ALU
The picture: a box with two input wires (A, B) and one output wire. Whatever numbers arrive on A and B get combined this tick, and the answer leaves on the output wire at the end of EX.
Why the topic needs it: forwarding is literally "which wire feeds ALU input A?" — the register file, or a shortcut from a later stage. The mux (§5) that chooses is the whole trick.
5. Pipeline latches, RegWrite, and the mux
Between each pair of stages sits a latch — a wall of tiny boxes that snapshots everything at the end of a cycle so the next stage sees it next cycle.
The picture: the forwarding mux sits right in front of ALU input A. Three wires arrive — (1) the normal value from the register file, (2) a shortcut from EX/MEM, (3) a shortcut from MEM/WB. A selector picks the freshest correct one.
Why the topic needs it: the parent's forwarding formulas are just the selector logic for that mux. Decoded:
- means AND — all three must be true.
- "the ahead-instruction actually writes a register" (
RegWrite), and - "it isn't the junk register
$0" (rd ≠ 0, because writing$0means nothing), and - "the register it writes is exactly the one I want to read" (
rd = rs).
When all three hold, flip the mux to take the shortcut.
6. Branches, PC, and "resolve"
The picture: a road with a fork. The PC is the arrow saying "go here next." At a branch we reach a fork but the signpost (condition result) isn't lit until the branch reaches EX. Meanwhile IF has already grabbed the next 2–3 instructions down one road — possibly the wrong one.
Why the topic needs it: the branch penalty = the instructions we fetched down the wrong road and must flush (throw away). Predicting the fork direction early is what §4 of the parent is about.
7. Probability & the CPI formula's symbols
The parent's CPI formula uses , , . These are just fractions and counts.
Why the topic needs it: this is the scoreboard. Every mitigation (predict-not-taken, 2-bit predictor) is judged by how much it shrinks , hence CPI.
Prerequisite map
Ready to go deeper? See Pipelining basics — 5-stage MIPS, Datapath and control signals, and the parent topic note. For the scoreboard math, Amdahl's Law and CPI analysis; for filling stall slots, Compiler instruction scheduling; for the advanced fix, Out-of-order execution and Tomasulo and Caches and memory hierarchy (why lw is slow).
Equipment checklist
Cover the right side and test yourself:
One tick where all hardware does one step, then advances together
The tiny named box holding one number inside the CPU
$t0)Register that is always 0 and never written
$0 / $zeroIn add $t1,$t0,$s1, which is the destination?
$t1 (rd)The five pipeline stages in order
The stage where the ALU runs
The stage where lw actually gets its data
The stage where a result is written into a register
LATCH.rd notation means
The 1-bit flag "does this instruction write a register?"
A hardware switch that picks one of several input wires
What means in the forwarding condition
Why we check rd ≠ 0 before forwarding
$0 is always zero; forwarding it would be meaningless