Intuition The one core ideaYour program speaks in pretend addresses (virtual) but your RAM only understands real addresses (physical), and turning one into the other normally costs several slow memory trips. The TLB is a tiny notebook that remembers the last few translations so the CPU can skip the slow trips almost every time.
Before you can read the parent note TLB — structure & miss handling , you need to own every symbol it throws at you. This page builds each one from nothing — plain words, then a picture, then the reason the topic can't live without it.
Imagine every byte of memory has a name. There are two naming systems for the same byte.
Definition Virtual address (VA)The address your program uses. It's a promise, not a location — like a PO box number. Your program thinks it owns a huge, private, tidy chunk of memory starting at 0 Virtual Memory .)
Definition Physical address (PA)The address the RAM chip actually uses — a real seat number in a real row of memory cells. Multiple programs share the same RAM, so their virtual addresses must be quietly redirected to different physical seats.
Intuition Why two systems at all?If every program used raw physical addresses, program A could scribble on program B's memory, and no program could assume where it starts. Virtual addresses give each program a clean private world; the hardware secretly maps that world onto the shared real RAM. That secret mapping is what the whole topic is about.
Everything below is built from bits . A bit is one switch: 0 or 1. A group of bits is read as a number in base 2.
2 n n 2 n doubles the count (each new switch either stays or flips). So 1 2 2 4 12 4096
log 2 ( x ) log 2 ( x ) how many bits does it take to name x It undoes 2 n 2 12 = 4096 log 2 ( 4096 ) = 12
log 2 log bits , and every extra bit multiplies choices by 2 log 10 ( 4096 ) ≈ 3.6 log 2 ( 4096 ) = 12 is the offset width.
The mapping doesn't work byte-by-byte (too many bytes!). Memory is chopped into equal blocks called pages .
Definition Page and page sizeP page is a fixed-size block of contiguous addresses. Its size is P P P = 2 p P = 4 KB = 4096 = 2 12
p p = log 2 ( P ) inside a page. For 4 KB p = log 2 ( 4096 ) = 12
Intuition Why blocks instead of individual bytes?If we redirected each byte separately we'd need a mapping entry per byte — billions of them. By moving whole pages, one mapping serves 2 p
Because memory moves in whole pages, a virtual address naturally splits into which page and where inside it .
The bottom p of an address: they say where inside the page a byte sits. Look at the yellow low bits in the figure.
Definition VPN — Virtual Page NumberThe remaining top bits of a virtual address: they say which page (the blue high bits). If a virtual address has V VPN bits = V − p , offset bits = p .
Definition PFN / PPN — Physical Frame NumberThe top bits of a physical address — which real block of RAM (a "frame") the page landed in. A frame is just a page-sized slot in physical RAM.
Intuition Why the offset is NEVER translatedMoving a whole page to a new frame is like moving a whole apartment building to a new lot. Your apartment number inside the building doesn't change — only the building's street address does. So the offset (position inside the page) passes through untouched; only VPN → PFN gets translated. This is why a TLB entry only needs to remember the page mapping , and why it can be tiny.
Worked example Reading a 48-bit VA with 4 KB pagesV = 48 p = 12
Offset = 12 Why? Anything below the page size can't change under translation.
VPN = 48 − 12 = 36
Number of possible pages = 2 36 exactly why page tables are multi-level and why we cache with a TLB.
The whole game is a lookup: given a VPN, find its PFN, then glue the untouched offset back on.
Definition The mapping VPN → PFNA rule that says "page number 5 currently lives in frame 27." All these rules together form the page table (see Page Tables (Multi-level) ). The TLB is a small fast copy of the most-recent such rules.
≪ x ≪ p x p 2 p p
∣ 1 positions), a ∣ b
Worked example A concrete address (4 KB pages,p = 12 = 0x12345678
Offset = 12 = 3 = 0x678 Why 3 hex digits? Each hex digit is 4 12/4 = 3
VPN = = 0x12345
Say the mapping gives VPN 0x12345 → 0x0ABCD
PA = ( 0x0ABCD ≪ 12 ) ∣ 0x678 = 0x0ABCD678
The TLB is a cache, so you must own three cache words first. (Full treatment: Cache Memory & Associativity .)
A small, fast memory that keeps copies of things you used recently, betting you'll use them again soon.
A hit = the thing you wanted was already in the cache (fast). A miss = it wasn't, so you pay the slow path to fetch it. For a TLB: a hit means the VPN→PFN rule was cached; a miss means you must go read the page table.
h h 0 1 1 − h
Common mistake "A TLB miss is the same as a page fault"Why it feels right: both mean "not found here." The fix: a TLB miss means the rule wasn't cached but still exists in the page table (nanoseconds to fetch). A page fault means the page isn't in RAM at all and must come from disk (milliseconds) — that's Page Faults & Demand Paging . A miss can lead to a fault only if the page table itself says the page is absent.
Two programs can both use VA 0x400000 different frames. The TLB must not confuse them.
Definition ASID / PCID — Address Space IDA small tag stamped on each TLB entry saying which program owns this rule . On lookup the CPU matches the VPN and the ASID, so entries from different programs coexist without a full flush. This is what makes Context Switching cheap.
To flush the TLB means throw away its entries. Without ASIDs you'd have to flush on every program switch (stale rules would be dangerous). With ASIDs you rarely flush — a big saving.
log base 2 gives bit count
page size P equals 2 to the p
split address into VPN and offset
virtual vs physical address
cache hit miss and ratio h
TLB is a cache of mappings
TLB miss handling and EMAT
Read it bottom-up: bit arithmetic feeds the address split, the split feeds the mapping, the mapping plus cache-thinking plus ASIDs give you the TLB, and the TLB plus its miss-cost give you the parent topic.
Cover the right side and answer out loud.
How many distinct things can n 2 n
What does log 2 ( x ) The number of bits needed to name x
For a 4 KB 12 log 2 ( 4096 ) = 12
Given V 2 p V − p
Why is the page offset never translated? Moving a whole page doesn't change where a byte sits inside it; only the page's location (VPN→PFN) changes.
What does PFN ≪ p Shifts the frame number into the high bits (multiply by 2 p p
Why can we use ∣ Their 1 bits never overlap, so OR just merges the two non-overlapping bit-groups.
Difference between a TLB miss and a page fault? Miss = mapping not cached but still in the page table (ns); fault = page not in RAM, fetch from disk (ms).
What is h 1 − h h 1 − h
What does an ASID let you avoid on a context switch? A full TLB flush — entries from different programs coexist by owner tag.