Intuition The one core ideaEach CPU core keeps private high-speed copies of memory to avoid slow trips to main memory — but copies of the same address can silently disagree the moment one core writes. Cache coherence is the hardware rulebook (and MESI is one such rulebook) that tags every cached copy with a state so that, for any single address, there is either one writer or many readers — never both at once .
Before you can read the parent note MESI protocol , you must own every word it throws at you. This page builds each one from nothing, in the order that lets the next one stand on the previous.
A core is one independent instruction-executing engine inside the CPU chip. A "quad-core" chip has four of them running at the same time, each with its own small memories.
Definition DRAM (main memory)DRAM is the big, slow, shared pool of memory — think of it as the single warehouse every core ultimately shares. It holds the official value of every address, but reaching it costs roughly 100 nanoseconds , which is hundreds of wasted cycles for a multi-GHz core.
A cache is a small, fast, private copy of a slice of DRAM, sitting right next to a core. Reading from it costs a few cycles instead of hundreds. The catch: a cache is a copy, not the original.
Look at the figure. The amber warehouse in the middle is DRAM. Each cyan box beside a core is that core's private cache. Notice that address X can appear in three places at once — that duplication is the entire reason coherence exists. If those copies drift apart, the cores disagree about reality.
Intuition Why the picture mattersEvery symbol in the parent note is about which box holds a valid copy of an address, and whether that copy is fresher than the warehouse. Hold this picture; everything else decorates it. See Cache basics — tags, sets, lines for how the cache is organised internally.
A cache line is the fixed-size chunk (typically 64 bytes ) that a cache moves in and out as one indivisible block. You never cache a single byte; you cache the whole 64-byte line containing it.
Think of DRAM as a long ruler divided into 64-byte tiles. When a core touches any byte in a tile, the whole tile is copied into its cache. This is why two variables that happen to share a tile get tangled together — the seed of the "false sharing" trap later in the parent note.
Why does the topic need this? Because coherence is tracked and enforced per line, not per byte . Every state we meet next is a label attached to a line .
Definition Clean and dirty
A cached line is clean if it holds exactly the same bytes as DRAM. The warehouse and the copy agree.
A cached line is dirty if this core has written to its copy but has not yet pushed the change to DRAM. The copy is fresher than the warehouse; the warehouse is stale.
In the figure the clean line (top) shows matching values in cache and DRAM. The dirty line (bottom) shows the cache holding 9 while DRAM still holds 5 — the amber "STALE" flag marks the warehouse as out of date. Whoever holds the dirty copy owns the truth and must eventually hand it back.
Intuition Why this distinction earns its keepThe whole difference between MESI's M and E states is precisely dirty vs. clean . If you don't feel the word "dirty," those two states will look identical. See Write-back vs write-through caches for how a cache decides when to push dirty data back.
Write-back means: when a core writes, it updates only its own cache and marks the line dirty. DRAM is updated later — only when the dirty line is evicted or another core demands it. (The opposite, write-through , updates DRAM on every write and is too slow to be the default.)
Why the topic needs it: the parent note says "memory now stale (still 0), but that's fine; M owns the truth." That sentence only makes sense once you know writes go to cache first and to DRAM lazily.
A copy is stale when another copy of the same line has been written more recently. Reading a stale copy returns an old, wrong value.
Core 0 cached X = 5. Core 1 wrote X = 9 into its cache. Core 0's 5 is now stale — it points at the past. If Core 0 reads without checking, it gets 5 and the two cores literally disagree about one address. Preventing exactly this is the job of the whole protocol.
The interconnect is the shared wiring that links all caches and DRAM — historically a single bus (one shared wire everyone can hear), now a ring/mesh/directory that behaves like one. See Bus snooping and interconnects and Directory-based coherence .
Snooping means every cache listens to every transaction on the interconnect, even ones it did not start. When Core 0 announces "I want to write X," Core 1 overhears and reacts (e.g. throws away its now-stale copy).
The figure shows the shared bus as a horizontal cyan rail. One core broadcasts a request (amber arrow); the other caches are drawn with "ear" symbols — they all hear it and each decides how to respond. That overhearing is what lets private caches coordinate without a central boss.
Definition The broadcast messages you'll meet
BusRd — "I want to read this line" (a read miss).BusRdX — "I want to read this line with intent to write " (also called Read-For-Ownership / RFO).BusUpgr / Invalidate — "I already have a read-only copy; tell everyone else to drop theirs so I can write."Flush / Write-back — "Here is my dirty data; take it."
Single-Writer / Multiple-Reader (SWMR) is the rule MESI guarantees for every address, at every instant :
either exactly one core may write it (all others hold nothing valid),or any number of cores may read it (none may write),never one writer and other readers simultaneously.
Picture a single microphone (write permission) that only one core can hold, OR a broadcast that many can listen to. You cannot be talking on the mic while others are also reading a frozen script — that would let them read a value you're in the middle of changing.
Why the topic needs it: the four MESI states are nothing but cheap bookkeeping that keeps SWMR true. Every transition in the parent note is enforcing this one sentence.
Definition Coherence vs. consistency
Coherence is a per-address promise: everyone eventually agrees on the single timeline of values for X.Consistency (the memory model ) is a cross-address promise: it governs whether a write to X becomes visible before a write to Y.
MESI gives you coherence only . It does not order writes to different addresses — that still needs fences and atomic operations . The parent note's biggest "steel-manned mistake" is confusing these two; make sure you feel the difference now.
The parent note derives Average Memory Access Time. Here is each symbol, in words, before you see it in a formula:
Every symbol is a rate × latency ; nothing is magic. With these defined, the parent's
AMAT = t hit + p miss ⋅ t miss
Interconnect and snooping
Bus messages BusRd BusRdX Invalidate
Read it top to bottom: the physical boxes define the line , the line can be clean or dirty, write-back explains when it goes stale, snooping is how cores notice, and SWMR is the promise that the four MESI states finally enforce.
Cover the right side and answer aloud; if any stalls, re-read that section.
What is a cache, in one phrase? A small fast private copy of a slice of DRAM sitting next to a core.
Why does DRAM being ~100 ns force us to cache? A multi-GHz core would stall hundreds of cycles per access; caches make common accesses a few cycles.
What is the unit coherence tracks — byte or line? A whole cache line (typically 64 bytes), never a single byte.
Clean vs. dirty — one sentence each. Clean = matches DRAM; dirty = this core wrote it but hasn't pushed the change back to DRAM yet.
What does write-back do on a write? Updates only the local cache and marks the line dirty; DRAM is updated lazily later.
What makes a cached copy "stale"? Another copy of the same line was written more recently, so this one holds an old value.
What is snooping? Every cache listens to all interconnect transactions and reacts to ones it did not start.
Name the four bus messages. BusRd (read), BusRdX/RFO (read-to-write), BusUpgr/Invalidate (drop others' copies), Flush/Write-back (supply dirty data).
State the SWMR invariant. Per address at all times: exactly one writer or any number of readers, never both.
Coherence vs. consistency? Coherence = agreement on one address's timeline; consistency = ordering across different addresses — MESI gives only the first.
In AMAT, what is p coh The fraction of misses caused by another core invalidating your line (coherence misses).
