4.1.2
Intuition Ek-sentence wali pictureEk computer basically ek CPU hai jo instructions ("kya karna hai") aur data ("kis pe karna hai") ko memory se kheenchta hai. Agar dono ek hi pipe mein rehte hain, toh CPU ek trip mein sirf ek cheez le sakta hai. Harvard architecture CPU ko do alag pipes deta hai — ek instructions ke liye, ek data ke liye — taaki dono simultaneously fetch ho sakein.
Intuition Woh bottleneck jo yeh khatam karta haiCPU fast hai; memory slow hai. Ek single-bus design (von Neumann) mein, har clock pe CPU ko choose karna padta hai: ek instruction fetch karo YA data read/write karo — dono kabhi nahi. Yeh forced serialization hi von Neumann bottleneck hai.
Harvard ki bet: har ek ko apna bus aur apni memory do, taaki ek fetch aur ek data access same cycle mein ho sake. YEH kyun kaam karta hai: do independent wires ek saath do signals carry kar sakte hain; ek wire nahi kar sakta.
Definition Harvard architectureEk computer organization jisme instructions aur data ke liye physically alag memories aur buses hoti hain. CPU ke paas hota hai:
ek instruction memory + instruction bus (fetch ki jaati hai, usually read-only),
ek data memory + data bus (read aur write),
jisse har cycle mein ek instruction fetch aur ek data access parallel mein ho sake.
Definition Von Neumann (contrast)Ek single shared memory aur bus mein dono instructions aur data rehte hain. Simple hai, zyada flexible hai, lekin instruction fetch aur data access ko turns leni padti hain (von Neumann bottleneck).
Hum ek memory access ko 1 cycle maante hain. Socho N f
Von Neumann — har shared-bus cycle ya toh fetch ya data karta hai:
Har instruction ko 1 fetch cycle chahiye: N
Un f N ek aur cycle chahiye: f N
T vN = N + f N = N ( 1 + f )
Yeh step kyun? Single bus fetch aur data ko serialize karta hai, isliye unke cycle costs add hote hain.
Harvard — fetch (instruction bus) aur data (data bus) parallel mein chalte hain:
Saare N N
f N andar unhi cycles ke data bus pe overlap ho jaate hain → 0 extra cost (jab collide na karein).
T H = N
Yeh step kyun? Do buses → data access fetch ke "neeche chhup" jaata hai. Costs add nahi hote, woh overlap karte hain (sum nahi, max hota hai).
Speed-up:
S = T H T vN = N N ( 1 + f ) = 1 + f
Intuition Pure Harvard rare kyun haiPure Harvard mein aasaani se instruction memory mein program data ki tarah load nahi kar sakte, ya self-modifying code nahi chal sakta — buses sach mein alag hain. Isliye modern CPUs Modified Harvard use karte hain: ek single main memory (neeche von Neumann), lekin split L1 caches — CPU ke paas ek alag I-cache aur D-cache .
Result: programmer ko ek flat memory dikhti hai (flexible, von Neumann jaisi), lekin hot path ko Harvard ka parallel fetch/access milta hai (fast). Dono ka best.
Worked example Example 2 — Pehle forecast, phir verifyForecast: "Agar workload pure arithmetic on registers hai (f = 0 Verify: S = 1 + 0 = 1 Confirmed — jab data traffic hi nahi hai toh overlap karne ko kuch nahi, isliye Harvard ka doosra bus idle baitha rehta hai. Benefit memory pressure ke saath scale karta hai.
Worked example Example 3 — Width/address-space freedomEk 8-bit DSP 16-bit instructions store karta hai lekin 8-bit data. Harvard kyun help karta hai: alag memories ke alag word widths aur address sizes ho sakte hain — instruction memory 16-bit wide, data memory 8-bit wide. Von Neumann mein, ek bus ko ek hi width choose karni padti. Yeh kyun matter karta hai: tight, saste embedded designs (isliye zyaatar microcontrollers — AVR/PIC/ARM Cortex-M — Modified Harvard hain).
Common mistake "Harvard ka matlab do CPUs / do cores hain."Kyun sahi lagta hai: "Separate" + "parallel" multiprocessing jaisa sound karta hai. Sach yeh hai: yeh EK CPU hai jiske paas DO memory paths hain. Parallelism memory access mein hai, computation mein nahi. Fix: ek chef ko do delivery doors ke saath imagine karo, do chefs nahi.
Common mistake "Harvard hamesha von Neumann se fast hota hai."Kyun sahi lagta hai: zyada buses = zyada bandwidth = fast, obviously? Sach yeh hai: speed-up 1 + f f = 0 zero gain hai, aur extra hardware (do memory systems, pins, controllers) area aur paisa kharcha karta hai. Fix: Harvard tabhi jeetta hai jab overlap karne ke liye data traffic ho.
Common mistake "Harvard pe normal OS / compiler nahi chal sakta."Kyun sahi lagta hai: agar instruction memory read-only aur alag hai, toh program (jo data hai) load kaise karoge? Sach yeh hai: pure Harvard struggle karta hai, lekin Modified Harvard (unified memory pe split caches) programs ko data ki tarah load kar leta hai aur sab kuch chalata hai. Fix: pure aur modified Harvard mein fark karo.
Recall Feynman: ek 12-saal ke bachche ko explain karoEk chef (CPU) imagine karo. Use recipes (instructions) aur ingredients (data) chahiye.
Ek kitchen (von Neumann) mein pantry ka single door hai, isliye use recipe ke liye bahar jaana padta hai, wapas aana padta hai, phir ingredients ke liye dobara bahar jaana padta hai — ek trip mein ek cheez.
Harvard kitchen mein do doors hain: ek hamesha recipes laata hai, ek hamesha ingredients laata hai. Do helpers ek saath kaam karte hain, isliye chef kabhi wait nahi karta. Catch yeh hai: recipe-door usually one-way hoti hai (aasaani se naye recipes wapas andar nahi daal sakte), isliye zyaatar real kitchens ek clever mix use karti hain — chef ke paas alag doors, lekin peeche ek bada shared storeroom.
"H = Halves" : H arvard memory ko do H ighways mein H alve karta hai. Aur "two doors, one chef."
#flashcards/coding
Harvard architecture kaun si ek problem attack karta hai? Von Neumann bottleneck — instruction fetch aur data access ek shared bus ke liye compete karte hain.
Harvard architecture mein kya physically alag hota hai? Instruction memory + bus aur data memory + bus (aur aksar caches bhi).
Ek cycle mein Harvard CPU kya kar sakta hai jo von Neumann CPU nahi kar sakta? Ek instruction fetch karo AUR saath mein data access karo simultaneously.
Idealized Harvard speed-up formula, symbol ka matlab bhi batao? S = 1 + f f
Agar f = 0 S = 1
Modified Harvard architecture kya hai? Unified main memory (von Neumann-jaisi) lekin alag L1 instruction aur data caches — vN jaisi flexible, CPU ke paas Harvard jaisi fast.
Pure Harvard mein programs load karna / self-modifying code kyun awkward hai? Instruction memory alag (aksar read-only) hoti hai, isliye aasaani se program as data usme write nahi kar sakte.
Speed ke alawa alag memories ka ek practical advantage batao. Instructions aur data ke liye alag word widths / address sizes (saste, tight embedded designs).
Kaun si real chip families Modified Harvard use karti hain? AVR, PIC, ARM Cortex-M microcontrollers.
Steel-man: koi kyun soch sakta hai Harvard ka matlab do CPUs hai, aur fix kya hai? "Separate + parallel" multiprocessing jaisa lagta hai; fix — yeh EK CPU hai jiske paas DO memory paths hain.
Von Neumann architecture — single-bus design jisse Harvard contrast karta hai.Von Neumann bottleneck — woh exact problem jo Harvard target karta hai.CPU instruction cycle — fetch/decode/execute; Harvard, fetch ko data access ke saath parallelize karta hai.Cache memory — split I-cache/D-cache = modern CPUs mein Modified Harvard.Pipelining — stages overlap karna; Harvard memory pe structural hazards remove karta hai.Microcontrollers (AVR PIC ARM Cortex-M) — real-world Harvard/Modified-Harvard users.Memory bus and bandwidth — do buses effective memory throughput double kyun karte hain.
Fetch and data in parallel
